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2003-03-03 Synopsys upgrades VCS and Vera
The company has announced upgrades to its VCS 7.0 Verilog simulator and Vera testbench automation tool.
2002-10-17 Synopsys expands open-source offerings
Synopsys Inc. has released an open-source version of a switching power exchange format at its semiannual EDA Interoperability Developer's Forum.
2003-03-03 Novas adds assertion support to debugger
Novas Software Inc. has added OpenVera assertion support to its new Verdi Behavior-Based Debug System.
2002-10-01 'Religious' wars abound
Should resets be synchronous or asynchronous? Should synthesis handle buffer insertion? Should OpenVera assertions be added to System Verilog? All these questions have provoked controversies in recent weeks, the first two in E-Mail Synopsys Users' Group (ESNUG) postings and at our EEdesign site.
2005-06-02 Synopsys VCS NTB solution verifies Huawei ASIC designs
Synopsys Inc.'s VCS comprehensive RTL verification solution with Native Testbench (NTB) technology and comprehensive coverage has been adopted by Huawei Technologies for verification of complex broadband ASIC designs
2005-09-30 Synopsys testbench solution increases verification productivity
Synopsys announced Discovery Pioneer-NTB, a new SystemVerilog testbench automation tool that claims to increase verification productivity and improve the quality of complex SoC and IP designs.
2007-08-23 Synopsys left out in SystemVerilog OVM initiative
Synopsys was not invited to join the OVM initiative recently announced by Cadence Design Systems and Mentor Graphics.
2006-03-30 Synopsys announces platform support for Sun processor
Synopsys announced its Galaxy Design and Discovery Verification Platform support for Sun Microsystems' UltraSPARC T1 processor.
2002-09-18 Sugar language sweetens assertions
Three EDA vendors will announce support for the Sugar 2.0 formal property language, adding to a growing list of endorsements that suggests this new Accellera standard will be widely accepted.
2002-08-14 Load sharing speeds formal model checking
@HDL Inc. will announce support for Platform Computing Inc.'s Load Sharing Facility with its @Verifier-DP product.
2002-09-01 ICCAD adds panels, workshops for designers
This year's International Conference on Computer-Aided Design show will feature design-related papers and panels, as well as workshops on open source and open standards.
2002-07-25 Expanded conference aims to attract designers
The 2002 ICCAD will try to attract designers by featuring design-related papers and panels, as well as a workshop on open-source and open standards, organizers said.
2005-08-29 ESL tool tames one tough task: On-chip register design
Blueprint, an electronic system level tool from Denali Software, automatically generates and manages the vast number of on-chip control registers that users no doubt find themselves juggling.
2005-10-03 Denali spreads new word in ESL mart
With a missionary zeal to establish standards and design methodologies, Denali Software leaps into the ESL market.
2005-01-04 Aldec blends SystemC, HDL debugging
Aldec released Riviera 2004.12. New features include integrated SystemC and HDL debugging, assertion-based verification, and functional code coverage.
2008-01-21 'Open' is (not) just a four-letter word
There is presently a measure of "openness fatigue" permeating the industry, but that's because the term "open" has been far too often applied to products and organizations that are far from open in significant ways.
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