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| 2001-04-26 | Using the resolve optimizer with RF simulations in the Affirma analog design environment This application note describes how to use the Resolve Optimizer with SpectreRF to optimize Noise Figure and Conversion Gain of a mixer circuit. |
| 2011-09-19 | Power optimizer, microinverter market to grow by 2015 Although the market increased 500 percent last year, microinverters and power optimizers accounted for less than one percent of PV inverter revenues. |
| 2004-06-01 | Optimizer vows custom speed for standard blocks Startup Zenasis Technologies says its cell-based timing-optimization tool can analyze blocks of up to 600Kgates. |
| 2010-11-12 | CSSP platform has visual enhancement engine, digital optimizer QuickLogic Corp. announced production availability of the second member of the ArcticLink II VX CSSP solution platform, the VX4, featuring Visual Enhancement Engine and DPO PSBs with a Mobile Display Digital Interface. |
| 2005-01-27 | Blue Pearl releases RTL optimizer Blue Pearl Software has announced the release of its first product, Indigo RTL Analysis, for rapid functional closure. |
| 2002-10-02 | Teradyne to use Galaxy tools in tester platforms Teradyne has partnered with Galaxy Semiconductor to deliver test program development solutions for Teradyne tester platforms. |
| 2007-03-16 | Stir manufacturing into design effectively Semiconductor companies looking to maximize yield will need to deploy more effective methods to account for manufacturing effects early in IC development. |
| 2004-06-01 | Prolific offers tool to assure signal integrity Prolific announced that the latest version of its timing optimizer works with Synopsys' PrimeTime SI static tool. |
| 2009-06-04 | Power optimizers target solar PV systems National Semiconductor Corp. has started shipping its SolarMagic power optimizers, a new product that dramatically improves the performance of solar photovoltaic (PV) systems impaired by real-world conditions. |
| 2007-01-16 | Optimization improves analog IC performance Some new technologies that were developed over the past decade enable analog IC designers to easily set up and efficiently run optimization on their designs. |
| 2003-11-05 | Legra fields WLAN switch Armed with a parallel cryptography ASIC and a wireless-networking processor, Legra Systems Inc. will announce the debut of its switch-based WLAN products. |
| 2010-12-03 | DPO tech prolongs single-charge battery life in handheld devices QuickLogic Corp. announced that its Display Power Optimizer Technology has been field-proven to reduce total system power consumption by up to 36 percent in handheld consumer devices such as smartphones and tablets. |
| 2006-02-03 | Cadence unveils new silicon-proven full-chip optimization system Cadence Design Systems announced its new manufacturing-aware chip optimization product Cadence Chip Optimizer, which is a silicon-proven full-chip optimization system. |
| 2004-01-19 | 64-bit Linux speeds IC design tool ReShape is reporting significant speed and capacity increases for its PD Optimizer tool suite on 64-bit Opteron and Athlon processors running Linux. |
| 2010-10-08 | National Semiconductor, Suntech to jointly develop smart panel tech National Semiconductor Corp. is working with Suntech Power Holdings Co. Ltd to develop "smart panel" technology. The technology will merge National Semiconductor's SolarMagic power optimizer chipset into Suntech solar panels to enhance the power output of their solar systems. |
| 2010-05-13 | Duo improves industrial, digital signage visual quality QuickLogic has signed Data Display to bring the company's Visual Enhancement Engine (VEE) and Display Power Optimizer (DPO) technologies to the industrial and digital signage markets. |
| 2010-08-20 | CSSP optimizes power, display resolution QuickLogic Corp.'s ArcticLink II VX2 CSSP solution platform integrates a display power optimizer, visual enhancement engine and proven system blocks. |
| 2006-09-18 | Web accelerator, enterprise manager unveiled F5 Networks Inc. has integrated Swan Labs' Web acceleration tools into its own Traffic Management Operating System environment and is now rolling out Web Accelerator as both a standalone appliance and as a module for its Big-IP system. |
| 2007-03-28 | Tool taps clock gating for IC power optimization Claiming breakthrough technology in IC power optimization, Calypto Design Systems is announcing PowerPro CG, a tool that automatically adds clock-gating logic to RTL code. |
| 2005-03-03 | Timing analysis needs overhaul, speaker says New IC devices, circuits, and physical effects will drive a new generation of timing analysis tools, said David Hathaway, senior technical staff member for EDA at IBM Microelectronics, at a keynote speech at the Tau timing workshop here Monday (Feb. 28). |
| 2006-03-14 | TI DSPs power Yamaha's new AVRs Texas Instruments announced that Yamaha's three new audio/video receivers are powered by its Aureus DA7xx generation of high-performance audio DSPs, handling all of the products' audio functionality. |
| 2004-09-17 | Synplicity upgrades FPGA logic, physical synthesis tools Synplicity announced the latest version of its FPGA logic synthesis and physical synthesis software solutions. |
| 2007-08-22 | Smart selection of compilation options in DSP applications Smart selection of compilation options can yield a dramatic performance improvement in DSP applications. This article shows how to improve code size consumption as well as the consumption of other important resources. |
| 2001-05-16 | Sequence Design offers tool for timing closure Sequence Design has combined different technologies in a "design closure" product that can optimize timing and signal integrity concurrently before and after routing. |
| 2012-02-10 | Samsung, Cadence partner in nanometer SoC design The companies will collaborate on a design-for-manufacturing (DFM) infrastructure to tackle physical signoff and electrical variability optimization for 32, 28 and 20nm ICs. |
| 2006-06-28 | Routing solution speeds design to manufacturing The Cadence Precision Router speeds design and manufacturing convergence for advanced mixed-signal, analog and custom digital designs. |
| 2007-06-14 | Rivals play down threat of Mentor's Sierra acquisition Mentor Graphics' rivals—Synopsys, Cadence and Magma Design—regard Mentor's Sierra acquisition as a minimal threat, and their own positions in 65/45nm IC design as strong. |
| 2012-05-31 | Reference architecture speeds modem time-to-market Ceva's reference architecture for LTE-Advanced (LTE-A) and cellular modems leverages power management and system partitioning to enable a software-based LTE-A solution as small as 3.4 x 3.4mm. |
| 2012-05-30 | Reference architecture anticipates 802.11ac Ceva and Antcor jointly release a low power, WiFi 802.11ac reference architecture designed for multimode WiFi 802.11ac mobile stations requiring a 1.5 x 1.5mm die area. |
| 2007-05-28 | Re-synthesis solution cuts 24% die area California-based Nangate Inc. claims that its re-synthesis solution will provide digital IC designers with the advantages of full custom design implementation while preserving the benefits of cell-based design methodologies. |
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