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2007-01-26 Synopsys contributes virtual platform tech to OSCI
EDA software provider Synopsys Inc. has contributed a key technology for the development of Virtual Platforms based on SystemC to industry group Open SystemC Initiative (OSCI).
2003-09-11 OSCI group seeks IEEE nod for SystemC
The Open SystemC Initiative is looking to cement the language's legitimacy by submitting it to the IEEE for standards approval.
2003-09-02 New OSCI board strives for SystemC approval
The Open SystemC Initiative (OSCI) wants to cement itself as a viable language for large silicon platforms and SoCs.
2011-06-23 Accellera, OSCI team up unifies EDA standards
Accellera and OSCI are joining forces to create a single organization, a move that will accelerate development of system-level standards as well as chip design and verification standards.
2006-12-08 SystemC transaction-level standard released for review
Taking a step towards the interoperability of SystemC transaction-level models, the Open SystemC Initiative has released a draft SystemC Transaction-Level Modeling 2.0 kit for public review.
2001-04-01 SystemC revision drives toward synchronized system-level design
Synopsys and CoWare launches the SystemC to create a standardized dialect of C/C++ for both hardware and software design. SystemC provides a C/C++ class library that represents hardware concepts such as concurrency for designers to utilize.
2006-05-01 Summit Design offers 'personal edition' of SystemC IDE on Web
The Vista-PE, touting all the features of the full-fledged Vista IDE at the module level, hopes to help people bring up and explore SystemC.
2006-02-01 Language standards from IEEE open choices
Once seen as competitors, SystemC and SystemVerilog languages appear to be settling into largely complementary niches.
2003-11-24 ARM rolls out transaction-level SystemC models
ARM Ltd has announced the availability of the transaction-level SystemC models of its cores that are targeted for system-level verification.
2001-05-16 Questions for SystemC
OSCI is supposed to be an "open" and independent standards effort, but Synopsys still has total control over the license agreement.
2005-09-27 Modeling, design environment topples SystemC simulator limits
VisualSim SystemC Modeler from Mirabilis Design Inc. couples the OSCI-compliant SystemC v2.1 simulator to the core of the company's VisualSim simulation engine.
2007-02-08 VERTIGO project to work on TLM, RTL standards
The Commission of the European Communities within the Information Society Technology (I ST) area has launched a project to bridge the gap between system-level modeling and verification performed at the transactional level and the traditional RTL signoff description.
2003-02-28 SystemC seen accelerating simulation
SystemC is seeing increasing use as a way of accelerating simulation, according to speakers at the DVCon Design and Verification Conference.
2007-09-20 Synopsys delivers system-level library
Synopsys has introduced the DesignWare System-Level Library that provides SystemC transaction-level simulation models for assembling virtual platforms.
2006-07-13 Summit Design launches IP interoperability initiative
Summit Design announced the launch of its Intellectual Property Initiative, which aims to address IP interoperability issues at the system level.
2005-06-15 STMicro bares major breakthrough in SoC design
STMicroelectronics has revealed the publication of a book on chip design methodology.
2008-02-26 Rhines on EDA: End 'endless verification'
Walden Rhines of Mentor Graphics calls for a combination of formal methods, TLM techniques and intelligent testbenches to lower the cost of design verification.
2006-03-24 Renesas adopts ARM ESL design tools
ARM today announced that Renesas Technology is the latest ARM Partner to license the ARM RealView SoC Designer ESL solution.
2015-06-11 Realising true FPGA-based verification
The scale of the latest FPGA technology is making that valuable emulator speed-up possible, but without the capital and operating expense associated with the big-box.
2013-05-28 ProximusDA, ST team up for SoC TLM virtual prototypes
The collaboration combines ProximusDA's expertise in parallel code distribution with ST's deep knowledge of Transaction Level Modelling and advanced distributed-computing architecture.
2008-03-10 More groups push standards for virtual prototyping
New players are expected to push forward efforts to create standards for virtual prototyping as the next wave in system and software development, to allow tools and simulation models from various suppliers work together.
2004-04-20 Mentor links SystemC to emulation
Mentor Graphics has announced a "transaction based" interface between SystemC testbenches and its VStation emulators.
2008-09-30 Intel, Chartered criticize chip IP industry
The semiconductor intellectual property (IP) industry has been the virtual and ongoing punching bag in the IC business.
2006-01-25 Forte Design Systems unveils next-gen Cynthesizer
Forte Design Systems announced the availability of the next generation of its Cynthesizer electronic system level (ESL) synthesis product.
2007-02-27 EDA 'troublemakers' debate at DVCon
Confronted with provocative questions, DVCon EDA vendor representatives debated topics such as low-power standards, Cadence Design Systems' Skill language, and outsourcing to India.
2004-11-09 CoWare upgrades SystemC-based SoC modeling tools
CoWare released a significant revision of its SystemC-based ConvergenSC SoC design tools.
2009-10-05 Braving software-to-silicon verification challenges at 45nm
Software-to-silicon verification holds immense challenges at 45nm and beyond for system designers and tool vendors, with multiple paradigm shifts converging at the same time.
2012-06-01 ASTC, Tanner to partner in ASIC design
John S. Zuk, vice president for marketing & business strategy at Tanner EDA, specified that ASTC teams will be utilizing the complete Tanner EDA tool suite.
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