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2006-07-06 X-ray analyzer eases advanced chip packaging
Xradia said the MicroXCT is suited for the engineering and failure analysis of next-generation semiconductor packages, including multistacked die and flip-chip architectures.
2008-11-21 Wafer-level packaging achieves prominence
Wafer-level packaging, the fabrication of the IC package directly on the wafer, is finally getting exposure after many years of promises, according to an expert in the field.
2011-11-22 Wafer packaging fab opens in Taiwan
STATS ChipPAC has increased production capacity with the completion of its 300mm wafer bump and WLCSP facility.
2007-01-22 UTAC: China testing, packaging industry yet to mature
Singapore's United Test and Assembly Center said that mainland China's IC testing and packaging industry still lacks market potential despite having Taiwan-based companies transfer their business to the region.
2006-12-08 UTAC expands Thailand packaging operations
United Test and Assembly Center Ltd will pump more than $100 million into its Thailand operations over the next three years as it shifts more low-end packaging activities to the country.
2013-07-09 USHIO books its interposer stepper for 2.5D/3D packaging
The UX7-3Di LIS 350 has achieved a resolution of 2?m L/S on a 300mm Si wafer as well as an organic substrate and is able to address a warp or expansion/contraction of an organic substrate.
2002-07-05 Unitive adopts Semitool's packaging platform
Semitool Inc. has announced the delivery of its electroplating system product, the Advanced Packaging Platform (APx), to Unitive Inc.
2004-07-14 Two firms apply carbon nanotubes to chip packaging
Carbon Nanotechnologies Inc. (CNI) has agreed with Kostat Inc. to develop and commercialize conductive polymers for module trays, carrier tapes and other semiconductor packaging and chip and die delivery applications.
2003-07-07 TSMC, Amkor partner on flip-chip packaging
Amkor Technology has developed and qualified wirebond and flip-chip packaging for devices manufactured on TSMC's advanced low-k process technologies.
2011-04-11 TSMC enters chip-packaging arena
TSMC will soon open a bumping facility and offer silicon interposers and TSV technologies for 3D chips, but will remain focused on the foundry market and will not compete against subcontractors.
2008-08-11 Trio seeks to cut costs in chip packaging
Infineon has granted licenses for its embedded Wafer-Level BGA chip packaging technology to competitor STMicroelectronics as well as STATS ChipPAC to lower costs and achieve higher market acceptance.
2002-11-08 Toshiba SiGe HBTs have 34 percent smaller packaging
The MT4S100T and MT4S101T SiGe HBTs will now be available in the proprietary TESQ package that measures 1.2-by-1.2-by-0.52mm - 34 percent smaller than the 4-pin SOT-343 surface-mount package.
2003-12-10 Toshiba offers lead-free packaging
Toshiba America Electronic Components Inc. (TAEC) announced that many of its power semiconductor package types will be manufactured using either lead-free packaging or lead-free finishes.
2003-11-11 Toshiba MOSFETs feature full isolation packaging
Toshiba Corp. has developed a family of medium- to high-voltage, power MOSFETs that allows high speed switching with faster turn-off time.
2002-08-06 Toshiba EEPROMs feature 50 percent smaller packaging
The TC9WMB1FK 1Kb and TC9WMB2FK 2Kb I2C bus-based serial EEPROMs are shipped in a US8 package that is 50 percent smaller than current TSSOP and MSOP casings.
2004-01-23 Toshiba develops nine-layered packaging technology
Toshiba Corp. said it has developed a multichip package that can stack up to nine chips in its 1.4-mm high package.
2012-04-02 TI expands IC packaging options with bare die
The bare die program allows customers to order small quantities as low as 10 pieces for initial prototyping purposes, and larger quantities of full waffle trays for production purposes.
1999-12-24 Through-hole packaging reels, ammo packs, and taping specifications
This application note deals with the through-hole assembly packaging of devices on reels and ammo packs with tape specifications.
2010-02-23 Tessera, Nanium ink packaging license deal
Tessera Inc. has signed a technology licensing agreement with Nanium, S.A, formerly known as Qimonda Portugal.
2004-11-12 Tessera, Matsushita sign packaging agreement
Tessera Technologies Inc. has signed a technology licensing agreement with Matsushita Electric Ind. Co. Ltd (MEI), giving the Japanese consumer electronic supplier access to its IP portfolio of multi-chip and chip-scale packages.
2005-03-25 Tessera signs up Fujitsu as chip packaging licensee
Tessera Technologies Inc. has signed a technology licensing agreement with Fujitsu Ltd for packaging intellectual property.
2009-11-26 Terepac, IMEC unite for flexible packaging
Terepac's patented photochemical printing process places thinned silicon dies and passive components on flexible substrates.
2008-09-04 Tegal secures products, IP for 3D packaging, MEMS
Tegal Corp. has signed an agreement with AMMS and Alcatel-Lucent to acquire products and the related intellectual property, directed at advanced 3D wafer-level packaging applications.
2002-07-19 Tegal joins the IC packaging alliance
Tegal's membership is expected to strengthen APiA's position in the IC packaging and interconnect industry.
2001-06-04 Tape and reel packaging for LSM2 VCOs
This application note describes the tape and reel packaging used with M/A-COM's LSM2 package style voltage-controlled oscillators (VCOs).
2001-06-04 Tape and reel packaging for LSM1A VCOs
This application note describes the tape and reel packaging used with M/A-COM's LSM1A package style voltage-controlled oscillators (VCOs).
2005-11-11 Sumitomo backs packaging firm with $20 million
Quantum Leap Packaging Inc., a provider of electronics component packaging that uses liquid crystal polymer compounds, is to receive $20M in equity finance from Sumitomo
2005-09-21 Spansion, Atheros packaging solution reduces size of mobile phones
Spansion LLC and Atheros Communications Inc. have developed an innovative packaging solution that is designed to reduce the size of dual-mode cellular/wireless LAN (WLAN) mobile phones.
2012-07-16 Smart packaging electronics to be available by 2014
Thin Film and Bemis aim to produce a time-temperature sensor to be used by consumer goods by 2014.
2015-09-28 SiP, PVS tech enabled for TSMC InFO packaging
Cadence said the Allegro SiP design tools and PVS allow TSMC customers to cut the InFO design and verification cycle by offering an integrated solution that automates the design-rule checking (DRC) flow.
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