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2012-11-01 TSMC: Quad patterning likely alternative to EUV for 10nm
TSMC's chief technologist stated that quad patterning may be needed for 10nm process technology if extreme ultraviolet lithography is not available by 2015.
2001-01-01 Thick photoresist patterning for WLP applications
Solder bumps, gold bumps, copper posts and copper wires for redistribution in wafer-level chip-size packaging require a resist mold that is later electroplated to form the final metal structures in advanced interconnect technologies.
2010-03-02 SPIE Litho wraps with delays, double-patterning
The themes of this year's SPIE Advanced Lithography event were clear: D and Ddelays and double-patterning. Indeed, EUV is delayed. So is maskless. And nanoimprint is still stuck in R&D.
2006-02-27 Platform enables real-time patterning control for 65nm node
KLA-Tencor unveiled the K-T Analyzer lithography correctables platform to accelerate and improve advanced lithography cell qualification and control.
2014-03-20 Patterning technique reduces material coercivity
North Carolina State University researchers came up with a technique to reduce the coercivity of nickel ferrite (NFO) thin films by as much as 80 per cent by patterning the surface of the material.
2013-06-06 Parasitic extraction in the double-patterning age
Determining the impact of double-patterning on electrical sign-off can be better achieved by understanding how PEX tools have evolved to handle this challenge.
2013-09-30 Novel method enables sub-micron patterning in organic ICs
Fujifilm and Imec have developed a new photoresist technology that enables sub-micron patterning on large-size substrates without damaging the organic semiconductor materials.
2009-12-15 Nikon eyes litho rebound with double-patterning
Nikon Corp. is looking to regain share, especially in the upcoming double-patterning era, according to an analyst.
2006-02-14 New patterning synthesis solution for 65/45nm
Invarium unveiled DimensionPPC, a unified, full-chip process and proximity compensation product for patterning IC layouts at 65nm and below.
2010-08-13 New method for patterning graphene discovered
Researchers at Georgia Tech have discovered a method to pattern the effective mass of graphene, with a magnetic switch to turn the pattern 'on' and 'off'.
2012-12-21 Imec, Altera expand scope of patterning research
Imec and Altera will further evaluate the readiness and limits of various patterning, FinFET and novel interconnect technology options for use in FPGA products.
2016-02-12 GlobalFoundries, SUNY Poly open advanced patterning centre
The $500 million, five-year programme will accelerate the introduction of EUV lithography technologies into manufacturing to expedite next generation chip technology.
2008-07-22 EUV delays drive shift to double-patterning
With the probable delays for EUV lithography, ASML, Canon and Nikon are racing each other to capitalize on the shift towards double-patterning technology at the 32nm node and beyond.
2005-04-06 Equipment makers develop inkjet patterning for FPDs
Display equipment manufacturers are developing inkjet method patterning equipment to replace color filter exposure systems and OLED deposition processes for the next-generation technology.
2014-08-25 Are multi-patterning corners necessary for 16/14 nm?
Multi-patterning is the technique required for printing geometries that are smaller than the wavelength of light used in manufacturing can accurately resolve. Find out if it is indeed needed for 16-nm and 14-nm nodes.
2010-04-26 3D-patterning technique trumps e-beam litho
IBM Research claims that a 3D technique for patterning at the atomic scale can outperform e-beam lithography in speed and resolution, at lower cost.
2006-09-20 Tool limits need for immersion lithography at 45nm
Invarium will roll out new patterning-synthesis software this week, promising, among other things, to limit the number of advanced layers that will require immersion at 45nm.
2006-04-11 Silicon film, TFTs use micro-liquid processes
Seiko Epson and JSR claims to have succeeded in creating the world's first silicon film with liquid coating and inkjet patterning processes.
2003-09-11 Researchers reflect on maskless lithos
An invitation-only workshop has kicked off last September 8, to explore a form of maskless lithography based on arrays of micromirrors.
2009-03-02 Panelists skeptical on next-gen litho
Experts debated and sparred over the future of patterning during a panel discussion at the SPIE Advanced Lithography conference.
2003-01-29 NanoOpto receives ISO 9001:2000 registration
NanoOpto Corp. has received ISO 9001:2000 registration for its Quality Management System from American Systems Registrar, LLC.
2009-02-25 Intel: EUV litho roadblocks ahead
A top technologist at Intel Corp. warned that a lack of mask inspection gear for extreme ultraviolet (EUV) lithography is threatening the process' future viability in the market.
2009-06-23 Intel scales down 193nm litho to 15nm
Intel claims that it has pushed 193nm immersion lithography down to 15nmat least in the lab.
2014-01-16 Imec modelling tool estimates cost of chip technology nodes
Imec and AlixPartners are co-developing a cost modelling solution to assess the cost of advanced semiconductor technology options. This modelling will assess the cost of various patterning options for N10/N7 nodes, advanced packaging solutions, and 3D NAND memory.
2015-02-20 Imec improves defectivity to near single-digit values
imec and partners, Merck & Co Inc. and Tokyo Electron, have improved directed self-assembly defectivity, approaching single-digit values. Results will be reported at the SPIE Advanced Lithography conference next week.
2011-07-20 IC compiler configuration touted 20nm-ready
Synopsys has launched the IC Compiler-Advanced Geometry, a configuration of its IC Compiler physical design product which targets design support for double-patterning technology.
2011-09-01 GlobalFoundries tests 20nm chip
GlobalFoundries has manufactured a 20nm test chip utilizing design tools from other design companies such as Cadence Design Systems, Magma Design Automation, Mentor Graphics and Synopsys.
2010-02-26 EUV delay forces tool makers to check other options
EUV lithography is delayed again and is now targeted for chip production at the 16nm half-pitch node, leaving the industry to face the dreaded double-patterning or some variation of the technology.
2005-07-18 Chip interconnect draws designers, too
The eighth annual ITTC opens to a growing and unfamiliar level of attention, the event has already begun to reach beyond its normal audience, attracting chip designers as well.
2013-01-30 Cadence unveils Virtuoso Advanced Node for 20nm
Cadence Design Systems has taken the wraps off Virtuoso Advanced Node, which enables the development of complex mixed-signal chips.
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