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phase locked loops What is a phase-locked loop (PLL)? Search results

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What is a phase-locked loop (PLL)?
A phase-locked loop or phase lock loop (PLL) is a control system which generates a signal that has a fixed relation to the phase of a "reference" signal. A PLL circuit responds to both the frequency and the phase of the input signals, automatically raisin
total search64 articles
2001-09-27 The RC charge pump: A versatile RF library circuit for phase locked loops (PLL) and beyond
This application note describes the versatility of the RC Charge Pump token in SystemView's RF library to satisfy many design tasks.
2002-11-08 Phase Locked Loops (PLL) in High Speed Designs
This application describes the contruction of a phase detector in conjunction with a voltage controlled oscillator to create a frequency generator synthesizer
2000-06-29 Frequency/Phase comparator for phase-locked loops
This application note describes a phase comparator that permits PLLs to be constructed using LCA devices, which only require an external VCO and integrating amplifier
2005-06-13 VIA integrates Sandwork debugging tools into IC design flow
The analog and mixed-signal debugging tools from Sandwork Design Inc. have been incorporated into the IC design flow of Taiwan-based VIA Technologies Inc.
2006-12-08 True Circuits rolls out silicon proven 65nm analog IP
True Circuits Inc. has announced "silicon proven" phase-locked loop and delay-locked loop hard macros using TSMC's 65nm process
2011-10-14 Reduce yield fallout by avoiding over and under at-speed testing
Here's a look at the problems associated with SoC at-speed testing such as overtesting and under-testing. This article also provides suggestions on how to overcome them.
2006-02-10 PLLs feature 'best spur performance'
National Semiconductor Corp. introduced the LMX248x family of high-performance, power-efficient PLLatinum delta-sigma phase-locked loops.
2005-05-02 Limits of IP block strategy exposed
Analog IP must be offered within the context of a broader solution that includes tools, services and lots of support.
2006-12-07 Instrument tests clock circuits, PLLs, oscillators
Wavecrest is rolling out a family of instruments dubbed signal source analyzers for testing clock circuits, phase locked loops and oscillators.
2016-01-21 In pursuit of quiet: Noise in linear regulators
It is always better to make sure the noise levels are low enough for your needs without expensive trials. Find out how this can be achieved.
2004-12-15 IBM researchers discover servo control method for optics
IBM Corp. researchers from the company's server division and Thomas J. Watson Research Center have collaborated on an unusual project to bring the advantages of phase-locked loops to wavelength domains.
2014-10-16 How to improve FPGA comms interface clock jitters
Know how external phase locked loops can be used to resolve problems faced when dealing with clock jitter in FPGA-based high-speed communications interfaces such as SerDes.
2002-08-16 Hidden complexities of PLLs are revealed
Measuring PLLs in a quiet, low-noise environment can yield optimistic and misleading jitter results.
2005-03-16 Don't pay much for mixed-signal tools
Cost-effective analog tools work well with advanced digital tools. They will let you get better payback on your next SoC project and integrate into your design flow at just the right points.
2005-07-01 Analog EDA firm tackles PLL noise
Berkeley's PLL noise analyzer promises to shrink time-to-volume for discrete analog/RF chips and SoCs containing analog blocks.
2009-01-21 Implementing PLL reconfiguration in Cyclone III devices
PLLs use several divide counters and different voltage-controlled oscillator taps to perform frequency synthesis and phase shifts
2015-05-14 Connecting passive components to logic gates
By adding a few passive components, you can make circuits such as level converters, frequency multipliers, phase detectors, line drivers, and pulse changers
2005-02-18 Web downloadable design tool suite supports new LatticeEC FPGAs
Lattice announced the immediate availability of v4.2 of its web-downloadable ispLEVER-Starter programmable logic design tool suite.
2015-04-27 Verilog-AMS vs SPICE view for SoC verification
In this article, we comparatively analyse the usage of Verilog/Verilog-AMS and SPICE views from the perspective of data converters and clocking IPs in an SoC.
2015-02-12 Verilog-AMS vs SPICE view for power management
Verilog-AMS is a behavioural abstraction of the circuit that sacrifices accuracy for the sake of run time, while SPICE does exactly the opposite. Here's a comparative analysis from a power management perspective.
2002-09-30 TSMC supports Barcelona in 90nm node-based products
Barcelona Design Inc. intends to develop products at the 90nm technology node.
2005-11-18 Triple ADCs geared for video
Texas Instruments' new pair of 8bit and 10bit triple analog-to-digital converters provide up to 165MSPS.
2000-02-01 The future of mixed-signal design
I hear two contradictory things regarding mixed-signal IC design. One set of voices says the systems-on-chip (SoC) of the future will be large mixed-signal systems, and the proportion of these being built will double from about 33 percent currently to 66 percent by 2005. The other set of voices says everything will be big digital chips constructed in ever-deeper submicron CMOS, in that the ASICs of the future will use as many 15 million logic gates, but that the analog and mixed-signal circuitry will be left off-chip.
2012-03-21 Taking advantage of MCU sleep modes to boost energy savings
Learn about the different MCU modes that allow energy conservation.
2006-01-26 Synthesis tool combines advantages of flat, hierarchical design
It's one thing to design individual blocks for large systems-on-chip and another to tie them together into a working device. Sierra tackles the latter challenge with its Pinnacle Chip Assembly solution.
2004-11-10 Synopsys, UMC, join ARM, National for low-power SoC demo
EDA tools vendor Synopsys Inc. and foundry chipmaker United Microelectronics Corp. (UMC) have joined the power management initiative first announced by National Semiconductor Corp. and ARM Holdings plc in November 2002 and again in October 2003.
2004-05-24 Synopsys releases design platform upgrade
Synopsys launched an upgrade to its design platform that delivers across-the-board improvements in run-time, capacity, QoR, silicon technology support and turn-around time.
2013-08-19 Silicon Labs unveils fully SyncE-compliant clock
The Si5328 is touted by the company as the industry's lowest jitter, lowest power and most frequency-flexible timing solution for high-speed networking equipment based on the SyncE standard.
2012-05-29 Signal chain basics: Understand spurious signals in high-speed DACs
Here's how to develop tactics and techniques for troubleshooting this likely problem.
2005-12-09 Regulator IC extends adaptive power management
National's LP5550 is the first digitally-controlled EMU for handheld consumer products that implements the company's PowerWise architecture for adaptive voltage scaling.
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