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2005-06-07 Three tout more nimble physical design
Three tool vendors are pitching breakthroughs in IC physical design in advance of next week's Design Automation Conference
2002-11-08 Synthesis-friendly RTL called key to first-pass design
To achieve first-pass timing closure on complex ASICs, designers must ensure their chip architecture design and RTL design are physical synthesis-friendly.
2006-01-26 Synthesis tool combines advantages of flat, hierarchical design
It's one thing to design individual blocks for large systems-on-chip and another to tie them together into a working device. Sierra tackles the latter challenge with its Pinnacle Chip Assembly solution.
2004-09-17 Synplicity upgrades FPGA logic, physical synthesis tools
Synplicity announced the latest version of its FPGA logic synthesis and physical synthesis software solutions.
2005-03-17 Synopsys unveils 'next-gen' compiler for physical design
Synopsys unveiled a physical design solution, which the company claims provides leading-edge performance and already carries endorsements by key IC suppliers
2005-10-11 Software offers graph-based physical synthesis into FPGAs
Synplicity has expanded its Synplify family of FPGA synthesis tools with Synplify Premier software
2007-07-11 RTL synthesis tool eases chip-level interconnect design
Claiming a new approach that helps solve problems with chip-level interconnect, Cadence Design Systems is announcing a new component of its RTL synthesis tool, the Cadence Logic Design Team Solution
2007-05-28 Re-synthesis solution cuts 24% die area
California-based Nangate Inc. claims that its re-synthesis solution will provide digital IC designers with the advantages of full custom design implementation while preserving the benefits of cell-based design methodologies
2004-05-17 QuickLogic FPGAs supported by Magma synthesis tool
QuickLogic has announced that Palace, the Magma physical synthesis tool for programmable logic devices, now supports its mWatt Eclipse II and Eclipse FPGA products.
2005-03-01 Physical synthesis in structured ASICs
How does a physical synthesis tool help ease front- and back-end design flow issues? Read on.
2002-03-01 Physical synthesis for complex FPGAs
This news article discusses how with the number FPGA system gates growing to more than 10 million, designers should optimize their designs to meet narrow market windows.
2002-10-16 Monterey adds Synplicity synthesis to ASIC design
Claiming to have a full RTL-to-GDSII design flow, Monterey Design Systems has added logic synthesis to its Dolphin system
2013-12-23 Mentor to acquire Oasys' RTL physical synthesis platform
The move by Mentor seeks to help SoC/ASIC design teams to realize improved quality of results and faster turnaround time for today's complex SoCs, ASICs and IP blocks.
2004-09-20 Mentor synthesis tools also supports Xilinx Virtex-4
Following the lead of FPGA synthesis archrival Synplicity Inc., Mentor Graphics Corp. said its Precision RTL or Leonardo Spectrum synthesis tools also support the new Virtex-4 family
2004-09-17 Mentor synthesis tools also support Xilinx Virtex-4
Mentor said its Precision RTL or Leonardo Spectrum synthesis tools also support the new Virtex-4 family
2003-12-08 Mentor get "physical" with FPGA synthesis
Mentor Graphics will roll out what it calls the first "integrated" RTL and physical FPGA synthesis solution.
2007-09-27 Mentor fields vendor-independent FPGA synthesis tool
Mentor Graphics has released the Precision RTL Plus Synthesis, which significantly improves the way of designing FPGAs and dramatically increases designer productivity
2008-09-29 Mentor extends synthesis support for new Xilinx FPGAs
Mentor says that its suite of advanced synthesis products support Virtex-5 TXT FPGAs
2008-04-04 Mentor adds synthesis support to Xilinx FPGAs
Mentor Graphics reports that its suite of advanced synthesis products now supports Virtex-5 FXT FPGAs from Xilinx Inc
2003-04-30 Magma folds synthesis into integrated tool suite
Magma Design Automation has unveiled the Blast Create, a single tool that combines silicon virtual prototyping, RTL, and analysis.
2005-04-07 Logic synthesis 'dying
Standalone logic synthesis will disappear and fold into physical design, said Rajeev Madhavan, Magma Design Automation CEO, at a keynote speech.
2003-04-11 Cadence makes another synthesis play, buys Get2Chip
Cadence Design Systems Inc. is once again trying to break Synopsys Inc.'s death grip on the ASIC synthesis marketshare, announcing that it has acquired Get2Chip Inc. for an undisclosed amount
2003-05-30 ASICs added to Synplicity's synthesis line
Synplicity Inc. will expand into ASIC physical synthesis with a tool that competes against offerings from Synopsys, Cadence and Magma.
2006-12-13 Synthesis tool meets complex CMP design rules
The new synthesis tool from Blaze DFM Inc. inserts dummy fill patterns into a design layout and is said to optimally meet complex CMP design rules without requiring complicated scripts
2004-08-12 Synthesis suite targets unconventional designs
FTL's Merlin is a tool suite that includes behavioral synthesis from VHDL or SystemVerilog; analog synthesis from VHDL-AMS or Verilog-AMS; and analysis and simulation
2007-04-24 Synthesis solution boosts IC performance
Synopsys released the Design Compiler 2007 synthesis solution, which extends topographical technology to accelerate design closure for designs utilizing advanced low-power and test techniques, to boost designer productivity and IC performance
2002-07-18 Synthesis of nanoparticles coming into focus
Scientists are fast gaining control over the building of tiny particles, accomplishing nanoparticle synthesis in both inorganic and organic chemistries. University of Arkansas researchers here have devised a
2002-08-02 Synopsys claims speedup for Physical Compiler release
Synopsys Inc. has announced a new release of Physical Compiler that it claims to offer a twofold run-time speedup and an average 6 percent improvement in quality of results
2008-05-09 Run practical power network synthesis
Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are commonly designed as custom switch cells of fixed sizes. The method described in this article avoids this unrealistic assumption and introduces the concept of a "fake via" to enable power network synthesis using existing EDA tools
2013-05-23 Performing synthesis-aware clock analysis
Read about a tool that performs clock structure analysis by tracing complex clock nets and visually presenting them to designers.
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