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2007-07-09 USB-based sensors operate even without power meter
Agilent Technologies Inc. releases the Agilent U2000 Series of USB-based power sensors, which operate without power meters or extra hardware modules
2007-03-28 Tool taps clock gating for IC power optimization
Claiming breakthrough technology in IC power optimization, Calypto Design Systems is announcing PowerPro CG, a tool that automatically adds clock-gating logic to RTL code
2005-06-02 Tool brings power analysis to virtual-prototyping phase
Bringing power analysis into the IC virtual-prototyping phase, Silicon Dimensions will announce the latest version of Chip2Nite, a design-planning tool aimed at logic designers
2003-06-02 Tool analyzes power dynamically, at cell level
Apache launched its 2nd product designed for power analysis, the RedHawk-SDL.
2004-07-01 Tool analyzes power across IC, package
Sigrity's XcitePI simulates power grids on the package plane to examine power integrity issues occurring between ICs and packages
2004-09-20 Tektronix industrial power option complements new DSO
Tektronix released its TPS2PBND Power Bundle, an industrial power option to complement the new TPS2000 series of Digital Storage Oscilloscopes
2002-06-11 Synplicity bolsters ASIC tools with power-analysis purchase
Moving to bolster its efforts in the ASIC tool market, Synplicity Inc. has purchased signal-integrity and power-analysis technology from startup Iota Technology Inc. for $4.1 million in cash and roughly 221,000 shares of stock.
2004-06-17 Synopsys low-power solution supports 90nm designs
During the DAC 2004, Synopsys announced that its Galaxy Power offers the industry's first comprehensive low-power solution for today's advanced, high-performance 90nm designs
2004-04-30 Synopsys keynoter cites crosstalk, power challenges
Crosstalk and power are extremely difficult problems to solve, and will require significant changes to the existing chip design flow, according to Li-Pen Yuan, R&D director for extraction and signal integrity at Synopsys
2002-10-28 Swept adjacent channel power analysis on digital TV amplifiers
The application software described here provides swept Adjacent Channel Power analysis, using AMIQ and SMIQ for signal generation and FSP, FSU or FSE for signal analysis, on power amplifiers used in digital TV systems.
2015-03-30 Significance of RTL architecture to power analysis
Learn about the advantages of a well defined RTL architecture for power estimation and analysis through a case study of a FIFO design.
2009-09-02 Sequential analysis ensures accurate power measurement
Calypto Design Systems Inc. has developed what it touts to be the most accurate register-transfer level (RTL) power analysis capability by applying its patented sequential analysis technology.
2004-01-06 Sequence wins power, inductance patents
Adding to its patent portfolio, Sequence Design has been awarded U.S. patents for RTL power analysis and extraction of parasitic mutual inductance.
2005-10-17 Self-learning switching DC/DC converters meet smart power
A handful of lossless current-sensing techniques are available today but their accuracies still do not compete with the traditional series sense-resistor schemes.
2008-05-09 Run practical power network synthesis
Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are commonly designed as custom switch cells of fixed sizes. The method described in this article avoids this unrealistic assumption and introduces the concept of a "fake via" to enable power network synthesis using existing EDA tools
2011-11-14 RTL sol'n yields ultra low-power design
The RTL Power Model predicts IC power behavior at the RTL level with consideration for how the design is physically implemented
2008-10-24 RTL power analysis enhances process geometries
Sequence Design has integrated "timing-aware" RTL power analysis features to its PowerTheater power analysis and prototyping tool.
2013-01-25 Reduce power estimation time from weeks to hours
Find out how to automatically generate a chip design's gate-level waveform from the RTL design environment without having to bring up the gate-level environment.
2007-03-16 Reduce memory subsystem power consumption in handsets
Less attention has been given to memory components despite the fact that the power demands of memoryat least 20 percent of total power budgetare equal to the demands of the application processor. Reducing the power used by memory can significantly extend handsets battery life
2013-02-28 R&S RTO, R&S RTM oscilloscopes tweaked for power supplies
Rohde & Schwarz offers high end voltage and current probes as well as the new R&S RT-ZF20 deskew fixture, making it easy to measure delay differences.
2013-10-02 R&S bolsters power characterisation options for scopes
The R&S RT-ZD10 probe is ideal for the characterisation of switching power supplies with high clock frequencies, while the R&S RTO-K31 and R&S RTM-K31 options offer specialised measurement functions
2004-09-08 Power-grid analysis tool gets a revamp
Donald Bennett, a design engineer in Lochore, Scotland, is taking steps to make himself a one-man commercial EDA vendor.
2011-05-31 Power optimization tool reduces power by 60
Calypto has released version 5.0 of its PowerPro Platform, featuring new RTL power analysis capabilities.
2009-03-19 Power management for optimal design
This article describes a holistic approach for managing and optimizing the power in a design. Effective power management involves proper understanding the application of a chip, technology selection, design techniques and methodology
2007-06-18 Power analysis tool aims at 45nm, 65nm designs
Extending its IC power-analysis capability to include several emerging methodologies, Apache Design Solutions Inc. introduced RedHawk-ALP that provides dynamic power integrity analysis for power-gated memories, VTCMOS circuits with substrate back-biasing and on-chip LDO voltage regulators.
2008-10-16 Parallel tech simplifies system analysis, task execution
Mentor Graphics Corp. has launched a new task-oriented parallelism technology in the company's Olympus-SoC place-and-route system that provides timing analysis and optimization tasks to run in parallel
2010-07-28 Optimizing power in SoC designs
Current methods employed by designers for optimizing power are inefficient and unproductive, making it difficult to know when a design is fully power optimized
2012-07-17 Optimizing FPGAs for low power apps
Know the low-power design techniques for the families of 7 series FPGAs
2006-10-19 Optimal announces enhancements to SiP analysis suite
Optimal is announcing chip/package/PCB co-design support in the form of enhancements to its Optimal SiP Analysis Suite
2009-01-09 Next-gen dynamic power integrity tool rolls
Apache Design Solutions has announced RedHawk-NX, the next-generation of the company's dynamic power integrity tool that is said to handle designs of 500 million gates
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