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| 2001-05-24 | Using PrimeTime in LSI Logic's FlexStream design flow This application note outlines the procedures LSI Logic recommends to customers on performing static timing analysis using the PrimeTime analysis tool. |
| 2003-04-25 | PrimeTime tool steps up to 50 million gates A new release of Synopsys' PrimeTime tool claims a runtime performance boost of two- to seven-fold over previous releases. |
| 2009-02-17 | Primetime now enables 2x faster runtime Synopsys Inc. has added a flexible multicore processing technology and new runtime optimizations to the latest release of PrimeTime static timing analysis tool, enabling up to 2x faster runtime, the company said. |
| 2002-11-05 | TSMC adopts Synopsys EDA tools TSMC has qualified Synopsys Inc.'s signal integrity suite to address the design methodology for its 130nm and 90nm process technologies. |
| 2004-05-03 | Toshiba used Synopsys platform for SoC designs Synopsys has announced that Toshiba has taped out multiple 90nm SoC designs for its audiovisual and office equipment product lines using Synopsys' platform. |
| 2008-01-29 | Synopsys upgrades signal integrity analysis suite Synopsys has announced that the 2007.12 release of its PrimeTime suite has set a new performance standard for both static timing and signal integrity analysis, accelerating turnaround time and design closure for today's nanometer designs. |
| 2006-10-03 | Synopsys triples TetraMAX ATPG speed Synopsys said enhancements to its TetraMAX ATPG product enable a typical speedup of threefold or more in runtime performance across all design styles compared with the previous version. |
| 2004-06-17 | Synopsys low-power solution supports 90nm designs During the DAC 2004, Synopsys announced that its Galaxy Power offers the industry's first comprehensive low-power solution for today's advanced, high-performance 90nm designs. |
| 2004-06-01 | Prolific offers tool to assure signal integrity Prolific announced that the latest version of its timing optimizer works with Synopsys' PrimeTime SI static tool. |
| 2002-08-29 | Prolific joins Synopsys in-Sync, TAP-in programs Prolific Inc. has joined the Synopsys in-Sync and TAP-in programs to ensure interoperability of its ProLiquid software with Synopsys' PrimeTime and Library Compiler tools, and the Liberty modeling format. |
| 2004-04-29 | Nvidia GPU designed with Synopsys platform Synopsys has announced that Nvidia's new GeForce 6800 graphics processing unit was designed with Synopsys' Galaxy Design Platform. |
| 2007-03-09 | Fujitsu standardizes on Synopsys solutions for 65nm sign-off Synopsys Inc. announced that Fujitsu Ltd has standardized on Synopsys' PrimeTime and Star-RCXT products as the timing sign-off solution for its 65nm ASIC and COT design flows. |
| 2001-05-01 | Cadence's 'all-in-one' tool gets skeptic reviews Cadence's Integration Ensemble (IE) is the first single tool that can take a hierarchical chip design all the way from synthesizable RTL code through a GDSII layout file and designers are raising an eyebrow if it will perform as well as it promises. |
| 2008-05-26 | Spice simulator speeds past rival tools Legend Design's MSIM high-accuracy Spice circuit simulator runs five to 10 times faster than most popular Spice simulators when characterizing the CCS Timing Model under PrimeTime accuracy requirement. |
| 2004-12-17 | Winbond achieves silicon success with Synopsys design platform Winbond Corp. has achieved first-pass silicon success using Synopsys Inc.'s Galaxy Design platform for its latest 130nm, MPEG-4 multimedia chips. |
| 2005-02-15 | Users laud C design in DAC 'trip report' Engineers are warming to C language design tools, according to reviews in the Design Automation Conference (DAC) "e;trip report"e; released Friday (Feb. 11) by industry gadfly John Cooley. |
| 2008-06-05 | TSMC stirs IC designs using 40nm node Paving the way for next-generation chips, TSMC is set to roll out its latest design methodology for IC production at the 40nm node. |
| 2006-08-30 | Toshiba tapeouts 90nm IC with Synopsys compiler Synopsys announced that Toshiba has used the Synopsys IC Compiler physical implementation solution to tape out its next-generation TC90515XBG home digital network chip. |
| 2006-07-01 | Tool suite handles design complexity Altera Corp. recently launched its Quartus 6.0 tool suite, which includes a timing analyzer that's said to pave the way for next-generation 65nm FPGAs. |
| 2004-04-23 | Timing optimization rolls for logic designers Silicon Dimensions has released an add-on to its Chip2Nite floor planner, block design and analysis offering. |
| 2005-06-07 | Three tout more nimble physical design Three tool vendors are pitching breakthroughs in IC physical design in advance of next week's Design Automation Conference |
| 2007-11-09 | Synopsys, UMC co-develop 65nm reference flow Synopsys and UMC have co-developed a 65nm hierarchical, multivoltage RTL-to-GDSII reference design flow. |
| 2009-02-03 | Synopsys, ST team up on SI sign-off tools Synopsys Inc. and STMicroelectronics have agreed to join forces to accelerate the development of methodologies and flows for low-power and high-performance SoC timing sign-off to reliably unleash the full performance potential of advanced technology nodes. |
| 2015-11-11 | Synopsys, GlobalFoundries team up for 22nm FD-SOI sol'n The Synopsys Galaxy Design Platform, enabled for the GlobalFoundries' 22FDX platform, claims to offer FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies. |
| 2004-12-03 | Synopsys' Galaxy platform supports Sasken reference flow Synopsys Inc. has announced that Sasken, an embedded telecommunications technology solution provider, has used its' Galaxy design platform to develop a reference flow to enhance the implementation and signoff process for its complex designs. |
| 2006-10-31 | Synopsys unveils DFM tools for 45nm, beyond Synopsys has unveiled a new family of process-aware DFM products that analyze variability effects at the custom/analog design stage for 45nm and smaller designs. |
| 2004-03-18 | Synopsys takes another stab at FPGA synthesis Synopsys has tweaked its Design Compiler ASIC synthesis tool to enable designers to use the same tools and potentially the same design flow for ASICs and FPGAs. |
| 2004-11-23 | Synopsys supports Xeon processor with Intel EM64T Synopsys Inc. claimed to be the first EDA software company to support the Intel Xeon processor with Intel Extended Memory 64 Technology (Intel EM64T) for 64bit and 32bit computing with the Red Hat Enterprise Linux version 3 operating system using its Galaxy design and Discovery verification technology. |
| 2005-02-09 | Synopsys supports SUSE LINUX with verification platform Synopsys Inc. will support the SUSE LINUX Enterprise Server 9 operating system (OS) from Novell on both 32bit and 64bit x86 instruction sets for Synopsys' Galaxy Design and Discovery verification platforms. |
| 2004-09-03 | Synopsys solutions to support IPCore design flow Synopsys Inc. disclosed that China-based IPCore Technologies Corp. has signed a multi-million dollar agreement. |
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