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2003-06-05 TransEDA debuts property verification tool
TransEDA has announced a property and assertion capture and validation tool at the 2003 Design Automation Conference
2003-05-26 New EDA consortium promotes assertion language
Seeking to accelerate the adoption of the PSL, 13 EDA companies have joined together with two user companies to form the PSL/Sugar Consortium.
2002-05-03 Cadence supports Accellera specification language
Cadence Design Systems Inc. has revealed that it is supporting the standard property specification language defined by Accellera to enable assertion-based simulation and formal verification.
2005-01-31 Back to the language roots
Although SystemC has its place in the hardware-design process, it still can't compete with Verilog and VHDL.
2003-03-25 Averant enhances proprietary assertion language
With the new Solidify formal verification tool, Averant Inc. claims to have significantly enhanced its HPL property specification language.
2004-06-30 Safelogic rolls out new property checking solution
Safelogic announced a major new release of its property checking solution and extended simulator support for its simulator plug-in product
2006-01-02 SystemVerilog won't kill 'e' language
Backers of 'e,' which is nearing IEEE standardization, say that rumors of the language's death are exaggerated
2002-09-18 Sugar language sweetens assertions
Three EDA vendors will announce support for the Sugar 2.0 formal property language, adding to a growing list of endorsements that suggests this new Accellera standard will be widely accepted
2006-02-01 Language standards from IEEE open choices
Once seen as competitors, SystemC and SystemVerilog languages appear to be settling into largely complementary niches.
2006-06-01 IEEE standardizes 'e' language
The IEEE has put its stamp of approval on Cadence Design Systems Inc.'s "e" verification language, making it an open standard that anyone can use or support
2005-12-16 Wrestling functional verification
Experts have differing views on how the design process can be improved so as to diminish the need for verification.
2004-02-02 Synopsys, Cadence give nod to SystemVerilog changes
Enhancements based on feedbacks from vendors and users spotlighting some shortcomings in the current ver 3.1, will be implemented in SystemVerilog 3.1a.
2003-04-08 Safelogic VHDL tool sweetened with Sugar
Safelogic Verifier 3.1 product now supports PSL.
2006-11-16 Revised VHDL boosts IP security
The Accellera standards organization has approved a revised version of the VHDL specification, marking a huge step forward for the design language
2006-10-10 Revised VHDL adds IP encryption capability
Proclaiming a major step forward for the VHDL design language, the Accellera standards organization this week announced it has approved a revised version of the VHDL specification, which features Property Specification Language (PSL) assertions and IP encryption capabilities.
2011-11-03 Perform assertion-based verification in mixed-signal design
Understand how assertion-based verification can address the challenges in analog/mixed-signal verification.
2003-11-10 Formal tool adds hierarchical PSL support
Claiming to offer complete verification layer support for Accellera's Property Specification Language (PSL), Swedish EDA vendor Safelogic has announced v1.5 of its Verifier product.
2003-06-10 Accellera launches new verification standards
Accellera announced that its Board and Technical Committee members have approved four new standards for language-based design verification
2013-04-04 Accellera launches EDA, IP interoperability standardisation
The company formed a multi-language working group to create a standard and functional reference for interoperability of multi-language verification environments and components
2004-06-08 0-In tools support Accellera SystemVerilog 3.1a
0-In Design Automation announced products within its Archer Verification system that provide support for Accellera's SystemVerilog 3.1a design constructs and IEEE-1076 VHDL.
2003-12-17 0-In Design tacks on static verification capability
The latest release of 0-In Design Automation Inc.'s assertion-based verification tool suite lets users run a design through debugging prior to simulation, potentially bringing the debug tools into the design cycle much earlier.
2003-11-13 0-In assertion compiler has multilingual features
The company will announce an enhanced assertion compiler for its Assertion-Based Verification (ABV) tool suite.
2006-06-15 Spirit enters IEEE standards process
The Spirit standard for IP integration and reuse has entered the IEEE standards process with the formation of the IEEE P1685 working group.
2005-10-26 Researchers propose approach to cut design validation time
Five Indian researchers from the have proposed a new approach to formal property verification
2008-09-30 Intel, Chartered criticize chip IP industry
The semiconductor intellectual property (IP) industry has been the virtual and ongoing punching bag in the IC business
2008-06-24 India's VLSI design projects soar to greater heights
India logged 1,826 VLSI design projects last year, of which 1,027 were done in the captive centers of overseas companies, and the rest by domestic design service providers. A report noted that it expects the total number will rise to 2,283 by the end of 2008.
2006-07-31 Denali, Spirit Consortium ink IP-XACT collaboration
Denali Software said it would work with the Spirit Consortium on development of IP-XACT to ensure that the consortium data model is aligned with SystemRDL, the system description language for SoC design registers
2005-10-03 Denali spreads new word in ESL mart
With a missionary zeal to establish standards and design methodologies, Denali Software leaps into the ESL market.
2001-05-16 C++ backed for system-level design
The industry must solve the problems of a synthesizable and verifiable C++ subset that has extensibility despite language constraints and lack of transportable libraries
2008-06-02 AADL addresses system integration
With the increasing hardware diversity and complexity of embedded software systems, a model-driven development approach has become a viable method to address system-integration issues in the early stages of development. The architecture description language is suited for systems with challenging resource constraints and strict real-time requirements
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