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2001-01-01 Test coverage enhancements at the register transfer level
This technology article describes the RTL buffer insertion and fault grading that helps identify untested functions and low-fault coverage areas where added test vectors can be generated.
2001-04-01 SystemC revision drives toward synchronized system-level design
Synopsys and CoWare launches the SystemC to create a standardized dialect of C/C++ for both hardware and software design. SystemC provides a C/C++ class library that represents hardware concepts such as concurrency for designers to utilize.
2001-05-16 Syntax raises RTL abstraction level
A University of Toronto professor has proposed a new RTL abstraction syntax that he claimed can be implemented by a modest extension to traditional imperative programming languages.
2004-12-13 STMicro keynoter sings praises of transaction level modeling
Philippe Magarshack, group vice president of central R&D at STMicroelectronics, made the 20km journey down the mountain from Crolles to provide a keynote presentation to the IP-SOC 2004 conference, which opened here today.
2002-07-01 RTL, gate-level tools fill out floor plan flow
IC tool startup InTime Software launches an RTL and a gate-level floor planner to complement its architectural-level floor planner
2003-09-16 Register-transfer level design handoff is ready
Shrinking process nodes and tightened purse strings have made the venerable "gate-level design sign-off" unacceptable
2005-05-02 It's time to move DFT to a higher level
Today, the 'D' in DFT does not really stand for design. All too often, at the gate level, it stands for do-it-late
2006-03-20 Initiative launched to accelerate FPGA system level design adoption
Xilinx launched the ESL Initiative, a multi-faceted program aimed at making ESL design methodologies and tools more accessible to programmable system designers.
1999-10-01 Estimating IC power consumption at the RT Level
Chip complexity raises the power consumption of a device to unprecedented levels. In this light, moving power analysis to the front end of the design flow enables you to make critical power-saving decisions early on and avoids costly, time-consuming iterations through synthesis and gate-level analysis
2004-11-01 EDA requirement shifts to front-end, system-level
Five years ago, EDA companies were in Asia merely to provide a presence. Now more EDA companies are setting up or expanding their operations.
2012-04-03 Developing NAND flash controller with high-level synthesis
Read about the application of a commercial HLS tool to a NAND flash controller with an error correction code block.
2003-08-01 Design-for-test moves up to RT level
SynTest Technologies propelled its entire DFT flow up to the RTL with DFT-Pro Plus, thereby lessening the likelihood of errors.
2014-12-04 Calypto intros high-level synthesis tech to speed up design
The Catapult 8 with the configurable hierarchical design architecture is built on a completely revised architecture that expedites design and verification closure, pushing widespread adoption of HLS.
2013-07-30 Reduce SoC power use without high-level EDA tools
Read about several situations where high level design tools are not useful and are sometimes a hindrance
2013-05-09 Why stitch and ship is no longer workable
As the systems change, the stitch and ship methodology is leading to increased numbers of costly failures.
2011-05-25 Verification tool quantifies verification progress
OneSpin launched its first comprehensive automatic metric-driven solution that analyzes and measures formal verification progress and quality in register transfer level (RTL) designs.
2005-03-16 Transaction-based simulation using SystemC/SCV
Learn how SystemC/SCV speeds up simulation and verification cycles to provide overall project cycle with better quality results
2005-06-22 Synopsys, IBM collaborate on PowerPC processor models
Synopsys announced fully synthesizable versions of IBM's PowerPC 405 and 440 processors as part of the DesignWare Star IP program.
2013-10-22 Structural, reset faults in SoC designs (Part 2)
Know some of the basic structural issues in reset architectures used in advanced nanometre scale SoC designs.
2005-06-15 STMicro bares major breakthrough in SoC design
STMicroelectronics has revealed the publication of a book on chip design methodology.
2004-01-06 Sequence wins power, inductance patents
Adding to its patent portfolio, Sequence Design has been awarded U.S. patents for RTL power analysis and extraction of parasitic mutual inductance.
2004-10-08 Rohm design platform based on CoWare ConvergenSC
Rohm developed a platform named Real Platform based on CoWare's ConvergenSC, a System C-based SoC design environment for ESL design.
2013-01-25 Reduce power estimation time from weeks to hours
Find out how to automatically generate a chip design's gate-level waveform from the RTL design environment without having to bring up the gate-level environment
2004-11-01 Partnerships key to EDA success in Asia
Partnerships will have to be formed and nurtured, and EDA companies will have to be more involved in the actual design process to improve their tools.
2005-08-26 Open-Silicon joins TSMC's design center alliance
Fabless ASIC supplier Open-Silicon Inc. has joined Taiwan Semiconductor Mfg Co. Ltd (TSMC)'s design center alliance program.
2005-06-06 New power optimization tool includes leakage power estimation
Claiming an industry first, ChipVision Design Systems has introduced an electronic system-level power optimization solution with leakage power estimation capabilities
2005-05-05 Mentor Graphics extends Catapult C synthesis product
Mentor Graphics Corp. announced extensions to its Catapult C synthesis algorithmic synthesis tool, an electronic system level (ESL) design tool
2006-09-18 Leverage ESL with legacy RTL
Platform-based design lets designers automatically integrate ESL modules with existing RTL IP. John Wilson gives his tips and tricks.
2004-05-06 Jasper upgrades verification product
Jasper Design Automation will announce the latest release of its JasperGold product enabling what the company calls a provably correct design methodology.
2001-06-01 Extraction method verifies IP functions
To keep in pace with silicon technology advancement, verification of the reused custom logic against its original counterpart should be considered as an integral part of the reuse process.
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