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2005-08-16 Tool gets a handle on voltage changes
As a chip designer for Intel Corp., Srikanth Jadcherla spent a lot of time working on multivoltage designs. Now he's launched an EDA startup, ArchPro Design Automation Inc., which is rolling out what it presents as the industry's first multivoltage RTL simulation product.
2013-08-15 Tabula's stylus compiler adds SystemVerilog support
Verific's software serves as the front end to a wide range of EDA and field programmable gate array tools for analysis, simulation, verification, synthesis, emulation and test of RTL designs.
2003-06-27 Synplicity debugger supports latest FPGAs
Version 1.2 of Synplicity Inc.'s Identify RTL debugging software features increased functionality and support for the latest field-programmable gate arrays from Actel, Altera and Xilinx.
2005-06-10 Synopsys adds PowerPC processors to DesignWare library
Synopsys Inc. has begun to offer synthesizable versions of the PowerPC 405 and 440 processors belonging to IBM Corp. as part of its DesignWare intellectual property library, Synopsys said
2008-02-29 Sun taps China academe for Sparc IC design
Sun Microsystems and China's Ministry of Education have signed a three-year agreement to bolster education in IC design using Sun's Sparc microprocessor technology.
2004-04-21 Startup's tool adds hardware validation
Carbon Design Systems has expanded the capabilities of its DesignPlayer models to perform hardware validation as well as presilicon software validation.
2003-09-03 Startup eyes hard/software pre-silicon validation
A 15-person design automation startup staffed with verification veterans aims to make pre-silicon validation tools practical for the masses.
2011-05-16 Springsoft software adds advanced verification tech
Springsoft has integrated an advanced technology platform to its Certitude Functional Qualification System that will enable broader deployment of verification qualification methodologies.
2007-10-04 Security in silicon: A guide to secure, high-speed SoC devices (Part I)
Implementing security functionality on dedicated hardware enables designers to achieve higher throughput performance, lower power consumption and a higher degree of security over software-based implementations running on a general-purpose processor.
2002-06-05 RTL-to-GDSII flow shows signs of maturity
The RTL-to-GDSII design flow will take center stage at next week's Design Automation Conference in New Orleans, as several vendors show new technologies intended to solidify an all-in-one flow.
2002-11-26 Risks of customer-owned tooling send designers to ASICs
Like do-it-yourselfers who wished they had called the plumber or electrician instead of botching a home repair, chip makers seem to be having second thoughts about customer-owned tooling.
2001-05-16 Researchers team up for Java-based IP query tool
A collaborative effort is producing a new Java-based tool that promises to allow users to easily query IP repositories and commercial databases via the Web.
2005-06-06 Renesas selects Verific HDL component software
Renesas Technology Corp. has adopted Verific Design Automation's hardware description language (HDL) component software for use in its internal EDA environment
2004-05-10 Platforms key to cost reduction
The only way to continue the march of electronics innovation in the midst of sometimes bedeviling complexity is for the industry to focus on developing platform-based design methodologies using robust tools, the chief executive of Mentor Graphics Corp. said Wednesday, May 5, 2004.
2001-03-01 Peripheral model makes dual run
With complex embedded-system designs exceeding 1 million gates, verification has become the critical bottleneck in the design process.
2005-12-21 Partnership targets SoC designs in Greater China
ARC and Global Unichip's new partnership aimed at speeding time-to-market for Greater China's increasing number of fabless startup companies attacking the digital audio IC market.
2002-10-22 Open-source C compiler targets FPGAs
Seeking to eliminate the need for detailed hardware expertise for FPGA design, a research group at the Los Alamos National Laboratory developed an open-source C compiler for reconfigurable logic.
2005-04-18 New IP line offers first RTL cores for linear algebra
The new AccelCore line from AccelChip offers algorithm developers and hardware engineers the industry's first fixed-point linear algebra IP as standalone resistor-transistor logic (RTL) cores.
2003-03-12 NEC to integrate Tera Systems technology in ISSPs
NEC Electronics Corp. has selected Tera Systems Inc.'s TeraForm RTL Design Consultant and Virtual Prototype technologies to be included in its Instant Silicon Solution Platform OpenCAD design flow.
2005-08-23 MPU achieves 1GHz clock speed
The new high-end processor core from Toshiba is touted to be the first configurable microprocessor to achieve a 1GHz clock speed.
2003-12-08 Mentor get "physical" with FPGA synthesis
Mentor Graphics will roll out what it calls the first "integrated" RTL and physical FPGA synthesis solution.
2003-03-17 Low-power design can bring down product cost
EDA and design communities have often focused on the high-end market driven by networking equipment without considering power; this focus must change as the economics of low-power design will drive a new segment of the ASIC market.
2001-03-01 Logic suppliers seek ways to embed FPGAs
Driven by the convergence of communications, computing and consumer applications, SoC design complexity increases the time required to bring competitive products to market, putting a premium on design speed and flexibility.
2012-06-07 Linting solution speeds design to implementation
Atrenta's Fast Lint methodology for its SpyGlass RTL analysis and optimization platform claims a 4X to 9X speed improvement while still delivering accurate, low noise results.
2004-06-01 Jasper upgrades verification product
Jasper has announced its JasperGold product that enables what the company calls a "provably correct design" methodology.
2008-09-30 Intel, Chartered criticize chip IP industry
The semiconductor intellectual property (IP) industry has been the virtual and ongoing punching bag in the IC business.
2006-06-01 IEEE standardizes 'e' language
The IEEE has put its stamp of approval on Cadence Design Systems Inc.'s "e" verification language, making it an open standard that anyone can use or support.
2004-02-26 IBM, Tera claim RTL handoff flow
Tera Systems and IBM Microelectronics have begun offering what they call the first production-ready RTL handoff flow.
2005-12-19 IBM to offer 'zero-cost' PowerPC license to universities
IBM announced plans to make the specifications of the company's PowerPC 405 core freely available to researchers and academia.
2015-02-09 Hardware emulation: The most versatile of them all
Nowadays, one of the most popular verification tools is hardware emulation and it might remain so in the next few years. Here is a look at the reasons behind its eminent success.
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