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2011-08-22 | How to reset an FPGA Know the various reset options available for FPGAs, as well as their advantages and disadvantages |
2013-10-22 | Structural, reset faults in SoC designs (Part 2 Know some of the basic structural issues in reset architectures used in advanced nanometre scale SoC designs |
2006-01-25 | ST expands reset IC lineup ST has introduced a 20-strong series of 3-pin reset ICsthe STM18xx seriesin a continued expansion of its family of microprocessor supervisor and reset devices |
2003-11-28 | Murata thermistor with multi-layered structure Murata Electronics has developed a ceramic PTC thermistor that features a multi-layered structure |
2012-10-22 | Rohm's latest EEPROMs feature I2C, up to 1Mbit density Rohm's double cell structure prevents this by allotting two cells for each memory bit, connected in an OR configuration so that the second cell is able to operate upon failure of the first |
2015-05-11 | Verilog-AMS vs SPICE view for DDR, LCD verification In this instalment, we comparatively analyse the usage of both views from the perspective of DDR interfaces, LCD controllers and on-chip memories. |
2008-06-17 | Toshiba doubles 2025 CO2 emission reduction target Toshiba Corp. has revised its goal to contribute to global CO2 emission reductions that more than doubles its initial target and takes it up to 117.7 million tons a year by 2025. |
2007-09-03 | Tips for successful structured ASIC designs The use of structured ASIC for custom IC design is an increasingly attractive option. This article provides useful tips for structured ASIC designs. |
2011-09-02 | Three-axis gyroscope boasts 10.5mm3 footprint STMicroelectronic's L3G3250A three-axis analog gyroscope claims to be the first to meet the demand for smaller footprints in applications such as gaming and virtual reality input devices. |
2014-03-27 | The move to 100A at POL and beyond While current demand is beginning to exceed the 100A level at the point of load, adopting a SEPIC-fed buck topology could prove useful in improving power conversion efficiency and transient response. |
2014-08-01 | Testing resistive memory devices In this instalment, we will address issues related to characterisation and forming, as well as endurance testing for 1R ReRAM structures. |
2014-08-21 | Sampling 16-channel SAR with 8-channel PSoC Here is how to build a 1Mbit/s 16-channel successive approximation register-based ADC with a Cypress PSoC 4, which has a built-in SAR multiplexer but only supports eight channels. |
2014-05-13 | Reducing guesswork in ESD tests Transmission line pulse measurements on the front end of the compliance phase can minimise the guesswork. |
2013-07-30 | Reduce SoC power use without high-level EDA tools Read about several situations where high level design tools are not useful and are sometimes a hindrance. |
2013-12-11 | Recognizing the issues with phase change memory There are about half a dozen papers on phase change memory (PCM) devices at IEDM 2013, and most deal with known reliability problems associated with PCM. |
2015-12-24 | Recent revelations on non-volatile memory conduction There is a continuing work at IBM Zurich that has just provided us with new and important insights into non-volatile memory, as well as an intriguing mystery. Read this to learn more. |
2016-04-11 | Probing ReRAMs: Forming scaling, quantised conductance Learn about the new ReRAM challenges as an IMEC team have formed and characterised the electrical conductance and topology of some of the smallest ReRAM filaments ever reported. |
2016-03-16 | Probing ReRAMs: 3D filaments, brain-like functions Here's a look at a research on ReRAMs based only on the sub-oxides of silicon to make the case for the suitability of their devices for use as emulators of brain-like neural functions. |
2014-03-25 | Power trends take spotlight at APEC 2014 During this year's APEC, global players such as Fairchild, Intersil and Texas Instruments revealed their business plans and product offerings in anticipation of the power efficiencies demanded by next-generation electronic devices. |
2014-06-09 | Phase change memory: Multi-level to multi-tasking In the VLSI 2014 paper, a 4bit per cell will be presented, the equivalent of 16 levels. It is conceivable that such a memory could operate in a multi-tasking role serving two separate applications. |
2012-05-28 | PCM progress report no. 7: A look at Samsung's 8-Gb array Here's a discussion on the features of Samsung's 8-Gb array. |
2012-03-15 | PCM progress report no. 6: Recent advances in phase change memory (Part 2) The second installment of this two-part series tackles other recent developments in PCM, including fabrication of a 1 Gb PCM array with a 4F2 cell size. |
2012-03-01 | PCM progress report no. 6: Recent advances in phase change memory (Part 1) This series looks at some of the most recent phase change memory developments. Part 1 reviews structural and materials advances, focusing on both benefits and challenges. |
2012-02-23 | PCM progress report no. 5: Scaling issues Learn about the possible approaches to achieve the scaling necessary to make PCM a commercial success. |
2012-02-16 | PCM progress report no. 4: Simulating the brain This report explores the use of phase change memory to emulate a component of the brain, the synapse. |
2012-02-09 | PCM progress report no. 3: New direction with polyamorphic states Here's a review of Semyon D. Savransky's paper to evaluate a type of nonvolatile memory based on polyamorphous chalcogenide transformations. |
2011-04-11 | PCM progress report no. 2: Review of PCM-related activities in early 2011 In this report, the author explores the PCM-related activities over the first quarter of 2011. |
2011-02-03 | PCM progress report no. 1: Temperatures rise and constituents on the move Here's a look at the overall picture of phase change memory progress. |
2007-01-18 | PCIe 2.0 spec doubles transfer rate to 5GTps The PCI-SIG released the PCIe base 2.0 specification, which doubles the interconnect bit rate from 2.5GTp to 5GTps to support high-bandwidth applications. |
2014-06-30 | NV memory: Significance of filament size and shape Many presenters in VLSI 2014 are seeking to improve performance and increase the understanding of ReRAM/RRAM operation. However, there is still no clear winner when it comes to material or memory type. |
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