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2005-12-16 Wrestling functional verification
Experts have differing views on how the design process can be improved so as to diminish the need for verification.
2006-12-06 Wind River boosts Eclipse support in updated Workbench
Wind River Systems' Workbench 2.6 release lets users integrate Wind River tools into existing development projects or workflows, or install the tools into pre-existing Eclipse apps.
2006-03-22 Wind River acquires middleware provider
Strengthening its ability to support Internet-based embedded applications, Wind River Systems Inc. announced early this week that it has acquired Interpeak AB.
2005-12-16 Where are the tools for next node?
If you're an EDA tool provider, it would be hard to find a more demanding customer than STMicro's Philippe Magarshack.
2006-03-16 What-If tools for everyone
Here is a comprehensive tool set providing an iterative, what-if analysis that engineers can run before PCB layout begins.
2006-09-13 Virtuoso becomes a 'native' OpenAccess application
Cadence is rolling out a new version of its Virtuoso custom design platform this week. The release offers a constraint-driven design flow and is built on top of the OpenAccess database.
2006-11-29 Virtual prototype support rolls out
Bluespec Inc. will roll out within the week a new version of its Bluesim simulator that supports virtual prototyping for software development and hardware validation.
2007-01-09 Verilog simulator offers faster RTL, gate-level simulation
SynaptiCAD has released VeriLogger Extreme, a compiled-code Verilog 2001 simulator, priced at $4,000 on Windows platforms.
2007-01-31 Verification box exceeds 200MHz speeds
Gidel Ltd's Proc_SoC verification box claims to exceed verification speeds of 200MHz, thanks to a direct FPGA-to-FPGA interconnect scheme.
2006-04-17 Vendors warm to SystemVerilog
Despite Synopsys' skepticism, synthesis vendors appear strongly supportive of a proposed standard SystemVerilog synthesis subset.
2006-11-16 Valor eases design with collaborative tool
vShare will provide a centralized, scalable platform with secure access to DFM-related design information, including design reviews, design changes and manufacturing sign-off.
2006-09-18 U.S. EDA monopoly may wane
Recent developments in Europe may challenge U.S. dominance over EDA in years to come.
2006-12-08 True Circuits rolls out silicon proven 65nm analog IP
True Circuits Inc. has announced "silicon proven" phase-locked loop and delay-locked loop hard macros using TSMC's 65nm process.
2006-10-16 Transaction assertions boost Jeda NSCa suite
Jeda Technologies is adding transaction-level assertion to native SystemC assertion (NSCa), a verification automation tool suite introduced in February.
2006-07-01 Tool suite handles design complexity
Altera Corp. recently launched its Quartus 6.0 tool suite, which includes a timing analyzer that's said to pave the way for next-generation 65nm FPGAs.
2006-08-01 Tool startups bet on autonomy
Two analog/mixed-signal design automation startups recently stepped into public view, chasing a goal that has eluded most of their predecessors: building a viable, independent company that doesn't fold or end up being acquired.
2006-02-23 Tool generates verification plans from design specs
Severity One is starting to sell Relay, a tool that produces reusable, coverage-driven verification plans from textual specifications or user input through a graphical user interface.
2006-09-01 Tool compiles C source code to RTL
CebaTech Inc. recently announced plans to offer both TCP/IP intellectual property (IP) and the C-language compiler that was used to create it.
2007-01-10 Tool claims breakthrough in ASIC debugging
Claiming a breakthrough in ASIC debugging, Synplicity will release details about TotalRecall, which it says will bring full debug visibility to FPGA prototypes used for ASIC verification.
2006-12-18 Test tool optimizes data for IC yield
LogicVision Inc. touts its solution Yield Insight to provide "yield learning," a process in which test failure data can pinpoint potential yield problems.
2006-11-30 Telelogic upgrades UML modeling system
Telelogic AB is marketing the 3.0 release of Tau, a UML-based development system, as a "breakthrough" that will help bring model-driven development to enterprise IT apps.
2007-03-16 Take distinctive approach to IC verification
Richard Goering spoke with Hooman Moshar about Broadcom's distinctive approach to IC verification.
2006-01-02 SystemVerilog won't kill 'e' language
Backers of 'e,' which is nearing IEEE standardization, say that rumors of the language's death are exaggerated.
2007-02-21 SystemVerilog falls short for design
SystemVerilog is widely applied to verification, however, design use lags due to concerns about tool support.
2006-12-08 SystemC transaction-level standard released for review
Taking a step towards the interoperability of SystemC transaction-level models, the Open SystemC Initiative has released a draft SystemC Transaction-Level Modeling 2.0 kit for public review.
2006-04-03 SystemC assertions go 'native'
Jeda Technologies shelved its own Jeda verification language in favor of a new tool suite supposedly equipped with the industry's first 'native' SystemC assertion-based verification automation capability.
2006-12-13 Synthesis tool meets complex CMP design rules
The new synthesis tool from Blaze DFM Inc. inserts dummy fill patterns into a design layout and is said to optimally meet complex CMP design rules without requiring complicated scripts.
2006-12-06 Synthesis tool eases ANSI C code generation
By automatically generating C, Catalytic Inc.'s new synthesis tool claims to eliminate the traditional process of manual translation.
2006-01-26 Synthesis tool combines advantages of flat, hierarchical design
It's one thing to design individual blocks for large systems-on-chip and another to tie them together into a working device. Sierra tackles the latter challenge with its Pinnacle Chip Assembly solution.
2006-06-21 Synplicity pushing open IP encryption methodology standard
Synplicity developed a free, non-proprietary IP encryption flow that permits industry-wide interoperability and is offering this methodology to the EDA, IP and end-user communities.
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