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2001-09-14 How reliable is the routing in your SDH network?
This application note explains how to determine the reliability of complex SDH networks through path trace analysis using the ANT-20 Advanced Network Tester.
2009-03-05 Hardware tips for point-to-point system design: termination, layout and routing
This technical note is the practical companion to Micron technical note TN-46-06, "Termination for Point-to-Point Systems," which discusses transmission line theory and the effects of series resistance.
2007-12-06 GPON residential gateway enables Gbit/s IPv4, IPv6 routing
PMC-Sierra's MSP7160 GPON residential gateway delivers gigabit-per-second IPv4 or IPv6 routing, NAT and QoS features.
2000-11-27 General routing techniques with emphasis on PI6C10X clocks
This application note discusses some of the terms and problems faced by design engineers when using clocks in their systems. It also discusses the techniques to eliminate or alleviate such problems.
2004-01-16 Flow-based routing boosts MPLS service
This article introduces an original flow-based routing approach that represents a marriage of the best of both circuit and packet technologies, applicable to both IP and MPLS networks.
2004-05-03 Exploring the T640 routing platform
Juniper Networks T640 routing platform consists of two main architectural components: router and packet-forwarding engines.
2009-06-23 EDA software adds new bus routing option
Pulsic Ltd has introduced an upgrade to its physical chip design software suite, Unity 2009.1.
2003-07-02 Cypress NSE achieves 266MSps for routing apps
Cypress Semiconductor is sampling the Ayama 10000 NSE family of network search engines that is suitable for apps that require large routing tables.
2006-05-17 Connector module eases signal routing
Fujitsu connector modules increase I/O port density and available PCB space while simplifying high-speed signal routing.
2002-09-23 Cadence adds Plato routing engine to design flow
Cadence Design Systems Inc. is upping the ante in the RTL-to-GDSII IC design tool arena with the latest release of its SoC physical implementation tool.
2006-11-09 Broadcom Wi-Fi chip provides full Layer 3 routing
Broadcom Corp. has introduced an 802.11g Wi-Fi chip that integrates its 54g radio and a MAC block with an Ethernet switch and a MIPS processor, providing full Layer 3 routing.
2008-03-17 Bring DFM/DFY into the routing engine
In reality, DFM/DFY tools need to use a mixture of rules- and model-based techniques as appropriate. The solution is to bring DFM/DFY upstream into the design process; to create a design that is correct by construction; and to hand-off a design that is as manufacturing- and yield-friendly as possible.
2001-07-03 Applying Network Processors For IP Routing ACL, NET And DiffServ
This paper presents an abstract on how the new breed of network processors is applied to both traditional and new data networking devices.
2014-06-05 Address SoC routing congestion with 2.5D SiP
The best of both worlds approach that the electronics industry has come up with to solve a design dilemma is the System in Package (SiP) in a 2D package.
2004-02-06 Acterna software provides accurate fiber routing
Acterna has announced that fiber network operators now have a network management solution that makes it easy to retrieve, cross-reference and share information among multiple users.
2004-03-19 'Over the top' routing boosts PCB speeds
A new approach to PCB routing can boost chip-to-chip interconnect speeds to 20Gbps, dramatically speeding system performance, according to Joe Fjelstad, founder of technology startup SiliconPipe.
2004-04-01 Wireless mesh shares MP3 files
On-demand streaming MP3 will also end the annoyances of DJs, commercials, bad songs or searching for a few favorite tunes among a stack of CDs.
2008-09-16 Valuing substrate parasitics in RFIC designs
Often, there is a need to simulate RFIC designs with substrate parasitics to accurately represent high-frequency effects in actual silicon. Generally, parasitics appear from a chip's surface layers, especially from metallization routing and coupling, or from the RC parasitics of the silicon substrate.
2005-01-03 Utility evaluates empty spaces on chip designs
As IC feature sizes shrink, the amount of empty space on individual designs has grown. A utility program from Apex Design will help designers evaluate what they can do with that space.
2010-10-28 TranSwitch demos communications processors at Broadband World Forum
Carrier-class semiconductors maker TranSwitch Corp. is demonstrating its routing, security and VoIP at the Broadband World Forum Europe 2010 in Paris.
2007-07-02 Tame signal integrity in the fast lane
High-speed serial standards have created a demand for design teams to not only think about signal integrity but to also have an in-depth knowledge of how it will affect the performance and reliability of today's systems thus, engineers must first understand what affects signal integrity within a system.
2005-04-18 Synopsys unveils 'next-gen' compiler
The company introduces a physical design solution which it says provides concurrent clock tree synthesis, routing and yield optimization.
2002-06-14 Synopsys compiler handles >20 million gate designs
Synopsys Inc. has announced the availability of the Floorplan Compiler, a high-end hierarchical design planner that accommodates >20 million gate designs through smart partitioning.
2002-07-11 Startup preps router for leading-edge designs
EDA startup ViASIC Inc. hopes of giving vendors like Cadence Design Systems and Synopsys a run for their money in the standard-cell routing-tool market.
2012-07-17 SPSR market to approach $15.4B by yearend
Ovum reported that the global service provider switching and routing market is expected to improve on recent performance and grow 4.4 percent.
2001-03-30 Solutions For Speeding Up Communication Equipment's Time-To-Market
This paper highlights the challenges faced by communication equipment makers in transitioning to advanced IP-based technologies using the current development methods.
2002-08-02 Silicon Access samples 20Gbps network processor
2004-04-19 Service routers get chassis, QoS spin
Alcatel aims to reduce the size and expand the functionality of carrier networks with additions to its service edge routing product family.
2003-03-03 Selecting a CPU core for multi-CPU SoC designs
This article examines the many features of processor cores being considered for multi-CPU designs.
2002-07-31 Schott Optovance offers 2D VSCEL interconnects
Schott Optovance Inc. has introduced a 2D VCSEL transceiver interconnect to address the emerging market of 2D parallel optical transceivers.
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