Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > routing

routing Search results

?
?
total search1415 articles
2005-03-30 'Concurrent' IC design suite rolls
Synopsys rolled out IC Compiler, which concurrently runs physical synthesis, clock tree synthesis, placement, routing, yield optimization and signoff correlation.
2012-01-16 zSFP+ connector geared for 25Gb/s Ethernet
The 20-circuit connectors support 10Gb/s Ethernet and 16Gb/s fiber channel applications.
2003-08-27 ZNYX rolls GbE switch offerings
ZNYX Networks has announced that it is shipping its Intel NetStructure ZT 8102 switch, which delivers 16GbE ports in a CompactPCI 2.16 form factor.
2005-10-05 ZiLOG flash MCUs eye BLDC, AC induction motor control apps
ZiLOG launched its Z8 Encore! MC family, a new generation of flash MCUs targeted at sensorless Brushless DC (BLDC) and AC Induction motor control applications.
2006-05-31 ZigBee transceivers use TI SoCs
AeroComm is offering OEMs two ZigBee RF transceivers based on Texas Instruments' recently released IEEE-802.15.4 SoC and Z-Stack firmware.
2013-08-21 Zigbee IP spec for IPv6 6LoPAN wireless networks
Read about the evolution of IP-based solutions for wireless sensor networks and also the use of the new ZigBee Smart Energy IP stack.
2004-10-13 Zener diode arrays provide ESD protection for high speed I/O ports
CAMD unveiled what it claims as the industry's lowest capacitance families of Zener diode arrays for electrostatic discharge protection.
2002-10-16 Yageo offers 433MHz, 870MHz miniature antenna
Yageo Corp. has announced the availability of a 433MHz and 870MHz miniature antenna suitable for use in low-data transfer and unidirectional wireless apps.
2008-02-19 XPhase chipset delivers AMD CPU power solution
IR has introduced the IR3514 and IR3507 XPhase chipset for AMD parallel and serial VID (PVID and SVID) processors.
2014-03-11 Xilinx: 16nm multi-core chips in the works
Xilinx said it will integrate the future 16nm chips with its own UltraScale architecture, which was first featured in the previous 20nm chips.
2006-02-09 Xilinx upgrades PlanAhead tool
Xilinx announced version 8.1 of its PlanAhead software, a hierarchical design and analysis solution for Virtex-4 and Spartan-3 FPGAs.
2003-09-10 Xilinx upgrades ISE FPGA design suite
Xilinx Inc. has improved clock performance, software run-time and area utilization in its Integrated Software Environment FPGA design suite.
2007-02-05 Xilinx upgrades free ISE Webpack design suite
Xilinx has announced the immediate availability of the ISE WebPACK 9.1i release, the latest version of the company's free downloadable programmable logic design suite.
2006-11-06 Xilinx unveils new design solution for Virtex-5 LXT
Xilinx announced the availability of a complete logic design solution including an update to its ISE design tools for their newest Virtex-5 LXT Platform FPGAs.
2006-07-07 Xilinx unveils design tools for 65nm Virtex-5 FPGAs
Xilinx has announced the latest release of its design solution, the 8.2i ISE tool suite, now supporting the company's newest line of 65nm Virtex-5 domain-optimized FPGAs.
2013-12-12 Xilinx UltraScale FPGA boasts 50M equivalent ASIC gates
The company announced its 20nm portfolio of All Programmable UltraScale devices, along with documentation and Vivado Design Suite support.
2013-07-11 Xilinx tapes out 20nm FPGA device
The firm worked with TSMC to infuse high-end FPGA requirements into the TSMC 20SoC development process to result in the first tape-out of the ASIC-class programmable architecture: UltraScale.
2004-10-21 Xilinx smooths EasyPath to take on structured ASICs
Xilinx Inc. is taking another whack at competing structured-ASIC vendors with a revised EasyPath program that it says boosts yields and lowers the cost of finished FPGAs.
2007-02-09 Xilinx ships 65nm FPGAs for high-performance DSPs
Xilinx has announced initial shipments of its 65nm Virtex-5 SXT FPGAs optimized for high-performance DSPs.
2006-03-16 Xilinx releases Virtex-4 FPGA based DDR2 reference design
Xilinx announced the immediate availability of the Virtex-4 FPGA based 667Mbps DDR2 reference design delivering high bandwidth and reliable memory interface solution.
2007-01-18 Xilinx ISE upgrade shortens FPGA design cycles
Xilinx' ISE 9.1i design suite is optimized to meet today's leading design challenges: timing closure, productivity and power.
2008-05-15 Xilinx intros intuitive reconfigurable DSP solution
Xilinx has introduced the Virtex-5 SX240T device to its 65nm Virtex-5 SXT FPGA platform optimized for high-performance DSP.
2006-10-04 Xilinx extends 8.2i ISE to support Virtex-5 LX330 FPGA
Xilinx introduced a downloadable extension to the 8.2i integrated software environment Foundation tool suite, allowing access to the Virtex-5 LX330 FPGA.
2002-10-23 Xilinx delivers programmable crossbar solution
Xilinx's Crossbar Switch is a programmable parameterizable custom design device capable of implementing digital cross-point switching functions.
2006-06-29 Xilinx delivers design solution for 65nm FPGAs
Xilinx has released the 8.2i Integrated Software Environment (ISE) design solution supporting the company's 65nm Virtex-5 FPGAs.
2006-02-06 Xilinx announces new DDR2 reference design
Xilinx's DDR2-SDRAM interface uses the Virtex-4 ChipSync technology, a run-time calibration circuit that improves design margins and overall system reliability while reducing design cycles.
2004-05-14 Xelerated offers ICs, software extensions as 'virtual ASIC'
Xelerated is offering a series of co-processor chips and software extensions to Broadcom's StrataXGS architecture.
2002-10-01 X Architecture members deliver 130nm masks
X Initiative member companies Cadence Design Systems, DuPont Photomasks, and Numerical Technologies have successfully produced the first X Architecture photomask for the 130nm semiconductor process technology node.
2003-02-25 Worldwide SPR market reaches $1.9B in '02
The worldwide service provider routers (SPRs) market totaled $1.9 billion in 2002 as SPRs continue to form the basis for additional telecom services and next-generation infrastructure, said Dataquest Inc.
2004-05-17 Wireless sensor nets demand trade-offs
This article will analyze the design trade-offs between node duty cycle and system-level performance, pinpointing opportunities to improve power efficiency while maintaining network robustness and responsiveness.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top