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2007-01-09 Verilog simulator offers faster RTL, gate-level simulation
SynaptiCAD has released VeriLogger Extreme, a compiled-code Verilog 2001 simulator, priced at $4,000 on Windows platforms.
2011-11-14 RTL sol'n yields ultra low-power design
The RTL Power Model predicts IC power behavior at the RTL level with consideration for how the design is physically implemented
2012-12-24 Easing system simulation with hardware models
Hardware models can accelerate integration and system verification tasksif they are available early enough in the design flow.
2007-01-10 C-to-RTL compiler promises full-chip design
Startup CebaTech Inc. will roll out the C2R Compiler, a C-to-RTL compiler that promises to generate full-chip designs
2006-10-17 Aldec claims Verilog simulation speedup
Aldec's new Riviera-Pro 2006.10 HDL simulator promises to provide a 57 percent speedup for RTL simulation and a 250 percent speedup for gate-level and timing simulations over previous releases of the software.
2004-06-03 Adveda modeler connects RTL, SystemC simulation
Adveda introduced a model generator simulation add-on that places a SystemC or PLI wrapper around RTL code so Adveda's fast models can be used with established top-down and bottom-up verification environments.
2004-06-01 Adveda launches extension to RTL simulator
Adveda introduced its Univers Modeler, an extension to its RTL simulator, which generates a SystemC wrapper or a PLI/FMI wrapper around a native simulation model.
2014-11-18 Addressing the problem of X unknowns in simulation
The sheer complexity and common use of power management schemes raise the probability of an unknown X state in the design, translating into a functional bug in the final chip.
2007-02-08 VERTIGO project to work on TLM, RTL standards
The Commission of the European Communities within the Information Society Technology (I ST) area has launched a project to bridge the gap between system-level modeling and verification performed at the transactional level and the traditional RTL signoff description
2006-09-01 Tool compiles C source code to RTL
CebaTech Inc. recently announced plans to offer both TCP/IP intellectual property (IP) and the C-language compiler that was used to create it.
2003-11-11 SystemC tool 'automates' ESL-to-RTL design flow
Offering technology that it claims will automate the ESL-to-RTL design flow, startup SpiraTech Ltd. has announced Cohesive, a toolset that bridges multiple levels of abstraction
2003-02-28 SystemC seen accelerating simulation
SystemC is seeing increasing use as a way of accelerating simulation, according to speakers at the DVCon Design and Verification Conference
2001-05-16 Syntax raises RTL abstraction level
A University of Toronto professor has proposed a new RTL abstraction syntax that he claimed can be implemented by a modest extension to traditional imperative programming languages
2005-01-03 Startup promises clean RTL code
Stelar Tools claims that its first product will cut 30 percent off the time it takes to move a design from initial RTL code development to synthesis
2003-09-01 Recycle RTL testbenches to verify IP models
Future work in the area of reusing RTL testbenches to verify TLM blocks will focus on fully automating the process, including automatic fault checking
2002-12-23 PCB package adds impedance routing, simulation
Altium Ltd. has added impedance-controlled routing, VHDL simulation, and synthesis for its PCB design tool
2006-09-18 Leverage ESL with legacy RTL
Platform-based design lets designers automatically integrate ESL modules with existing RTL IP. John Wilson gives his tips and tricks
2004-05-12 Forte synthesis tool accelerates RTL delivery
Forte has disclosed that its Cynthesizer is the first behavioral synthesis product to offer an implementation path from SystemC to RTL, verification and co-simulation.
2003-06-10 Formal tools won't replace simulation
Formal verification is a valuable adjunct to simulation, but not a replacement for it, according to panelists at the Design Automation Conference
2004-10-07 EverCAD simulation software adopted by UMC
EverCAD Software disclosed that its ADiT software has been adopted by United Microelectronics Corp.
2004-06-01 EDA startup preps tools for RTL closure
Blue Pearl Software said its upcoming technology will identify and fix functional and DFT errors in RTL code, locate false paths and automatically generate timing constraints for synthesis
2006-05-26 Dongbu, Cadence offer RTL-to-GDSII reference flow
South Korean foundry Dongbu Electronics said that it has collaborated with Cadence Design Systems Inc. to jointly develop the DBE 130.2 reference flow.
2004-06-03 Cadence, CoWare partner on ESL-to-RTL verification
Last September's partnership between CoWare Inc. and Cadence Design Systems Inc. has yielded its first fruits, as the companies are introducing a new co-developed flow they claim will allow users of CoWare's ConvergenSC SystemC-based prototyping system to "seamlessly" transfer models built in SystemC and Verilog to Cadence's Incisive verification platform.
2005-01-27 Blue Pearl releases RTL optimizer
Blue Pearl Software has announced the release of its first product, Indigo RTL Analysis, for rapid functional closure
2004-06-08 Atrenta releases RTL checker
Atrenta's assertion-based functional analysis tool checks whether user RTL is functionally correct and fixes problems to minimize iterations between simulation and synthesis.
2013-03-25 Analyse RTL clock gating to cut processor power
The focus on clock gating and the fast turnaround of RTL analysis allow measurable power reductions for typical applications of X86 AMD core
2001-04-25 How to simulate RTL designs with LSS memory
This application note explains how to simulate designs with LSS's memory modules. It provides an overview of LSS's memory type, configuration, simulation environment, etc
2001-12-01 Deterministic simulation of an ARM core
This technical article discusses the deterministic and random testing techniques used to verify complex cores such as the ARM946E-S architecture.
2007-07-17 Xilinx releases free ISE WebPACK 9.2I
Xilinx has announced immediate availability of Integrated Software Environment (ISE) WebPACK 9.2Ithe latest version of the company's free downloadable programmable logic design suite.
2005-08-16 Tool gets a handle on voltage changes
As a chip designer for Intel Corp., Srikanth Jadcherla spent a lot of time working on multivoltage designs. Now he's launched an EDA startup, ArchPro Design Automation Inc., which is rolling out what it presents as the industry's first multivoltage RTL simulation product.
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