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2003-08-07 RTL tool provider snags $5.3M funding
Atrenta Inc., provider of RTL "predictive analysis" solutions, has secured $5.3M in series B venture capital funding
2006-04-07 Xilinx beefs up AccelDSP Synthesis tool
Xilinx announced the immediate availability of the new AccelDSP Synthesis 8.1 tool and AccelWare DSP libraries of algorithmic intellectual property
2007-01-09 Verilog simulator offers faster RTL, gate-level simulation
SynaptiCAD has released VeriLogger Extreme, a compiled-code Verilog 2001 simulator, priced at $4,000 on Windows platforms.
2009-01-21 Verification tool provides step-by-step approach
OneSpin Solutions has amended its software and packaged it in a way that supports a step-by-step approach for beginners.
2002-03-11 Verification tool enables rapid ASIC prototyping
Designed for creating ASIC and SoC prototypes using off-the-shelf FPGAs, the SpeedGate Direct System Verification environment addresses all hardware prototype creation and verification challenges.
2001-05-24 Using formality for RTL-to-gate in LSI Logic's FlexStream design flow
This application note describes procedures and recommendations for using the Formality formal equivalence checking tool for RTL-to-gate equivalence checking.
2004-08-31 UMC uses Mentor Graphics FastScan ATPG tool
The FastScan, an automatic test pattern generation tool, from Mentor Graphics Corp. has been selected for UMC's 130- and 90nm digital reference flow
2005-02-04 UMC adopts Magma extractor tool on 0.13?m process
United Microelectronics Corp. (UMC) has validated Magma Design Automation Inc.'s QuickCap NX extractor tool on its 0.13?m process
2004-12-21 Toshiba supports Cadence RTL compiler for ASIC design
Cadence Design Systems Inc. announced that Toshiba America Electronic Components Inc. (TAEC) has introduced a design kit to support its custom System-on-Chip (SoC) and ASIC customers using Cadence Encounter RTL compiler synthesis
2003-05-15 Tool vendor @HDL licenses solvers from IBM
@HDL has licensed formal verification technology from IBM Corp. and plans to incorporate the technology into its current product line in the coming months.
2007-03-28 Tool taps clock gating for IC power optimization
Claiming breakthrough technology in IC power optimization, Calypto Design Systems is announcing PowerPro CG, a tool that automatically adds clock-gating logic to RTL code.
2009-05-07 Tool simplifies on-chip interconnect design
EDA vendor Sonics Inc. has rolled out a new tool to ease the job of building on-chip interconnects using the ARM Amba bus
2004-03-17 Tool pinpoints false paths, steers designers away
FishTail Design Automation is targeting what sounds like a small niche, but the company says the potential benefits of its technology are huge.
2006-09-01 Tool compiles C source code to RTL
CebaTech Inc. recently announced plans to offer both TCP/IP intellectual property (IP) and the C-language compiler that was used to create it.
2005-06-02 Tool brings power analysis to virtual-prototyping phase
Bringing power analysis into the IC virtual-prototyping phase, Silicon Dimensions will announce the latest version of Chip2Nite, a design-planning tool aimed at logic designers
2005-12-08 Tool ARMs for SoC validation
Carbon Design Systems' SOC-VSP extends ARM's RealView SoC Designer to import "Carbonized" VHDL or Verilog RTL models
2004-07-12 Tensilica compiler automates RTL generation
Claiming to provide an increasingly attractive alternative to custom RTL blocks, Tensilica announced its Xtensa Processor Extension Synthesis Compiler
2003-07-10 Taiwan-based IC designer adopts Verplex tool
FMC SOTA Design Technology, a Taiwan-based design services company, has adopted Verplex Systems' formal verification software.
2004-04-02 SystemC tool adds top-down design
CoWare has added graphics-based front-end design software and other features to the System Designer tool of ConvergenSC
2003-11-11 SystemC tool 'automates' ESL-to-RTL design flow
Offering technology that it claims will automate the ESL-to-RTL design flow, startup SpiraTech Ltd. has announced Cohesive, a toolset that bridges multiple levels of abstraction
2002-11-08 Synthesis-friendly RTL called key to first-pass design
To achieve first-pass timing closure on complex ASICs, designers must ensure their chip architecture design and RTL design are physical synthesis-friendly
2010-05-11 Synthesis tool handles complex design verification
NextOp is bridging design and verification with the introduction of an assertion-based verification solution to automatically generate functional coverage properties from testbench and RTL
2006-12-06 Synthesis tool eases ANSI C code generation
By automatically generating C, Catalytic Inc.'s new synthesis tool claims to eliminate the traditional process of manual translation
2001-05-16 Syntax raises RTL abstraction level
A University of Toronto professor has proposed a new RTL abstraction syntax that he claimed can be implemented by a modest extension to traditional imperative programming languages
2003-11-06 Synplicity upgrades RTL prototyping tool
Synplicity Inc. has released a new version of its Certify ASIC RTL prototyping software with enhanced automatic pin multiplier technology, new compilers and mappers, and support for hardware-based FPGA prototyping systems from AMO and EVE
2008-04-21 Synplicity tips device-independent FPGA design tool
A device-independent IP configuration and system-level assembly environment has been introduced by Synplicity.
2004-06-01 Synplicity spins Xilinx-specific version of RTL debugger
Synplicity released a version of its Identify RTL debugging software with features targeting users of Xilinx's FPGAs
2003-01-10 Synplicity revamps ASIC synthesis tool
Synplicity Inc. is stepping up the competition against Synopsys, Get2Chip, and Incentia with its latest Synplify ASIC.
2015-03-27 Synopsys tool fast-tracks dev't of ASIC processors
ASIPs are deployed in various signal-processing intensive applications such as wireless base stations, mobile handsets, audio processing, image processing and cloud computing.
2003-03-03 Summit tool beefs up SystemC
Summit Design Inc. launched its Visual Elite 3.1 which included FastC to better reach out to HDL designers.
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