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What is RTL?

RTL stands for Register Transfer Level. It is a high-level hardware description language (HDL) used for defining digital circuits. The most popular RTL languages are VHDL and Verilog.

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2007-02-08	VERTIGO project to work on TLM, RTL standards The Commission of the European Communities within the Information Society Technology (I ST) area has launched a project to bridge the gap between system-level modeling and verification performed at the transactional level and the traditional RTL signoff description.
2002-10-01	Verplex: Solutions for correct RTL design implementation Taiwan started promoting electronics in the 1980s as part of its key economic development initiatives.
2007-01-09	Verilog simulator offers faster RTL, gate-level simulation SynaptiCAD has released VeriLogger Extreme, a compiled-code Verilog 2001 simulator, priced at $4,000 on Windows platforms.
2001-05-24	Using formality for RTL-to-gate in LSI Logic's FlexStream design flow This application note describes procedures and recommendations for using the Formality formal equivalence checking tool for RTL-to-gate equivalence checking.
2004-12-21	Toshiba supports Cadence RTL compiler for ASIC design Cadence Design Systems Inc. announced that Toshiba America Electronic Components Inc. (TAEC) has introduced a design kit to support its custom System-on-Chip (SoC) and ASIC customers using Cadence Encounter RTL compiler synthesis.
2006-09-01	Tool compiles C source code to RTL CebaTech Inc. recently announced plans to offer both TCP/IP intellectual property (IP) and the C-language compiler that was used to create it.
2004-07-06	Tera survey claims RTL handoff interest A survey of over 400 engineers, many of whom attended an RTL handoff symposium at the Design Automation Conference (DAC), reveals a considerable interest in the topic, according to Tera Systems.
2004-07-12	Tensilica compiler automates RTL generation Claiming to provide an increasingly attractive alternative to custom RTL blocks, Tensilica announced its Xtensa Processor Extension Synthesis Compiler.
2003-11-11	SystemC tool 'automates' ESL-to-RTL design flow Offering technology that it claims will automate the ESL-to-RTL design flow, startup SpiraTech Ltd. has announced Cohesive, a toolset that bridges multiple levels of abstraction.
2002-11-08	Synthesis-friendly RTL called key to first-pass design To achieve first-pass timing closure on complex ASICs, designers must ensure their chip architecture design and RTL design are physical synthesis-friendly.
2001-05-16	Syntax raises RTL abstraction level A University of Toronto professor has proposed a new RTL abstraction syntax that he claimed can be implemented by a modest extension to traditional imperative programming languages.
2003-11-06	Synplicity upgrades RTL prototyping tool Synplicity Inc. has released a new version of its Certify ASIC RTL prototyping software with enhanced automatic pin multiplier technology, new compilers and mappers, and support for hardware-based FPGA prototyping systems from AMO and EVE.
2004-06-01	Synplicity spins Xilinx-specific version of RTL debugger Synplicity released a version of its Identify RTL debugging software with features targeting users of Xilinx's FPGAs.
2002-10-01	Startup to open RTL-to-test bridge Nikhil Dakwala prepares the industry's first memory RTL-to-ATPG modeling bridge.
2005-01-03	Startup promises clean RTL code Stelar Tools claims that its first product will cut 30 percent off the time it takes to move a design from initial RTL code development to synthesis.
2005-06-24	ST cuts verification time with Synopsys VCS RTL solution STMicroelectronics has used Synopsys Inc.'s VCS comprehensive RTL verification solution to ensure verification completeness of 10 million-gate design targeted at TV applications.
2006-06-09	SoC tools promise seamless SystemC-to-RTL design flow Sonics' latest SonicsMX Smart Interconnect and SonicsStudio promise a seamless SystemC-to-RTL design flow that provides consistent SystemC or RTL versions of specific SonicsMX configurations.
2005-11-21	SMIC, Magma offering RTL-to-GDSII flow for 130nm SoCs Magma Design Automation Inc. and Semiconductor Manufacturing International Corporation (SMIC) have made available a validated reference flow based on Magma's Blast Create, Blast Plan Pro, Blast Fusion and Blast Power for system-on-chips (SoCs) targeted at SMIC's 130nm process.
2015-03-30	Significance of RTL architecture to power analysis Learn about the advantages of a well defined RTL architecture for power estimation and analysis through a case study of a FIFO design.
2011-01-20	RTL-to-GDSII reference flow launched Magma Design Automation announced the availability of a hierarchical RTL-to-GDSII reference flow for the Common Platform alliance's 32/28nm low-power process technology.
2002-06-05	RTL-to-GDSII flow shows signs of maturity The RTL-to-GDSII design flow will take center stage at next week's Design Automation Conference in New Orleans, as several vendors show new technologies intended to solidify an all-in-one flow.
2002-07-01	RTL, gate-level tools fill out floor plan flow IC tool startup InTime Software launches an RTL and a gate-level floor planner to complement its architectural-level floor planner.
2003-08-07	RTL tool provider snags $5.3M funding Atrenta Inc., provider of RTL "predictive analysis" solutions, has secured $5.3M in series B venture capital funding.
2006-12-21	RTL synthesis tool speeds up run-time Cadence Design Systems has released Encounter RTL Compiler version 6.2, which promises a 10 percent improvement in quality of silicon and a 30 to 50 percent run-time speedup.
2007-07-11	RTL synthesis tool eases chip-level interconnect design Claiming a new approach that helps solve problems with chip-level interconnect, Cadence Design Systems is announcing a new component of its RTL synthesis tool, the Cadence Logic Design Team Solution.
2011-11-14	RTL sol'n yields ultra low-power design The RTL Power Model predicts IC power behavior at the RTL level with consideration for how the design is physically implemented.
2013-12-03	RTL signoff: A design imperative "RTL Signoff" as an established concept has gained significance in the last year. However, writes Atrenta's Piyush Sancheti, does a commonly accepted definition of RTL signoff exist?
2008-10-24	RTL power analysis enhances process geometries Sequence Design has integrated "timing-aware" RTL power analysis features to its PowerTheater power analysis and prototyping tool.
2012-11-28	RTL analysis of FPGA using Grey Cell method Understand the two major issues in the RTL analysis space and the ways to address them.
2003-09-01	Recycle RTL testbenches to verify IP models Future work in the area of reusing RTL testbenches to verify TLM blocks will focus on fully automating the process, including automatic fault checking.