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2008-05-01	Use MSGQ module to optimize sRIO gains Serial RapidIO overcome limitations of traditional DSP I/Os by providing a high performance, packet-switched, interconnect technology which is very beneficial for complex DSP topologies.
2010-10-11	Switch advances SRIO ecosystem Integrated Device Technology reports on the adoption of its Serial RapidIO Gen2 switch for applications in wireless baseband, semiconductor processing, medical imaging, and radar and sonar markets.
2005-07-01	Industry sees promising market for sRIO While the parallel version of RapidIO has almost been the standard in most backplane designs, the serial version is relatively new in the design community.
2008-11-27	I/O module packs FPGA, four SRIO ports, PCIe Innovative Integration has announced the X5-COM XMC IO module. The module features a Xilinx Virtex-5 FPGA, four 4.125Gbit/ss serial Rapid IO (SRIO) ports, and a PCI Express host interface.
2006-03-10	DSP enables robust sRIO ecosystems Texas Instruments announced the availability of a TMS320C6455 DSP evaluation module and a DSP starter kit, both with a Serial RapidIO bus interface.
2008-10-01	AdvancedMC caters to wireless, SRIO interfaces CommAgility has released the AMC-V5F, a single width, mid-sized Advanced Mezzanine Card for AdvancedTCA and MicroTCA systems.
2013-02-18	MicroTCA Carrier Hubs upgraded to support MTCA.4 spec Kontron has recently upgraded its MicroTCA Carrier Hubs, offering the MicroTCA enhancements for rear I/O and precision timing.
2005-06-01	Interconnects: Evolution at high-speed Evolving interconnect technologies pose new design considerations in meeting desired data-processing system performance
2008-07-02	Enable DSP co-processing in FPGAs Today's ever increasing demand for high-speed communication and superfast computing in support of triple-play apps is creating new challenges for those who need to draw together a multitude of standards, components and networking equipment.
2007-02-01	Address SI issues in high-speed board design This article discusses some of the SI challenges and the factors associated with high-speed interface designs that are enabled with key features of a RapidIO switch.
2007-06-25	Platform leverages Serial RapidIO technology Freescale Semiconductor Inc. and Tundra Semiconductor Corp. have introduced a development platform that combines Freescale's multicore MSC8144 programmable DSPs with Tundra's low-power Tsi578 Serial RapidIO (sRIO) switch.
2005-08-02	Virtual instrumentation shapes up for industry demands Benchtop test equipment are here to stay, while virtual instrumentation test systems will push for more market acceptance as it continues to adapt to the changing needs of today's industry.
2014-05-05	VadaTech kits out MCH with 40GbE option, advanced clocking The MCH boasts up to four times boost in performance and enables highly flexible master/slave clock and time synchronisation to multiple clocking standards, leading to precision timing, aligned frequency/phase of the signals, and risk elimination involving packet loss due to buffer overflow.
2009-08-17	Utilizing extra FC credits for PCI Express inbound posted memory write transactions in PowerQUICC III devices This application note explains the procedures to utilize the extra FC (flow control) credits for PCI Express inbound posted memory write transactions, which is currently a hidden feature for all of the x8-capable Power QUICC III devices.
2009-06-22	Tool suite speeds up multiprocessor apps design Multiprocessor design company 3L Ltd has introduced the latest version of its Diamond multiprocessor tool suite.
2008-12-01	Surpass LTE requirements, goals Long Term Evolution presents a series of lofty goals, creating a set of challenges for technology providers, equipment manufacturers and service providers.
2008-10-17	Single-chip DSP integrates three 1GHz cores Texas Instruments Inc. has developed a new high performance multicore DSP that offers significant cost, power and board space savings.
2010-09-17	Scalable HD video solution supports more than 30 codecs Freescale moves video coding off servers and onto embedded processors for cost savings
2009-07-06	Quad transceivers claims lowest jitter National Semiconductor Corp. has released the DS50PCI401 and the DS64BR401 quad transceivers that increase backplane and cable reach up to 30 percent farther than competitive devices in data center servers and storage area networks.
2010-12-08	Programmable clock synthesizers break 100 femtosecond jitter barrier Micrel launched the first line of its next-gen ClockWorks Flex family the SM802xxx. The devices target both wireline and wireless apps. Micrel launched the first line of its next-gen ClockWorks Flex family the SM802xxx. The devices target both wireline and wireless apps.
2012-08-16	Partnership speeds multicore dev't on TI's TMS320C66x DSPs CommAgility and PolyCore Software teamed up to speed up multicore software development with tools for CommAgility's DSP boards using PSI's Poly-Platform.
2008-06-18	Packet switches tailored for high-bandwidth apps IDT recently expanded its family of switches with the addition of a higher performance and higher bandwidth device, which may be suitable to diverse applications ranging from 3.5G and 4G wireless infrastructure to next-generation enterprise storage and imaging applications.
2009-09-01	Multicore DSP supports 3G/4G wireless standards Freescale has unveiled the MSC8154 processor designed to add a variety of price, power and throughput options to Freescale's portfolio of high-performance DSPs based on StarCore technology.
2011-11-11	Multicore DSP geared for mission critical apps TI's C66x DSPs can be used in SDRs, radars and surveillance and imaging systems, as well as servers, video processing networks and security.
2010-08-11	MoSys, Radiocomp, GDA collaborate on wireless Serdes MoSys, Radiocomp and GDA Technologies have joined together to deliver a complete end-to-end connectivity solution, focusing on the 3GPP long term evolution (LTE) and 4G cellular base station component market.
2009-05-12	LatticeECP3 Serdes/PCS usage guide The LatticeECP3 FPGA family combines FPGA fabric, I/Os and up to 16 channels of embedded Serdes with associated Physical Coding Sublayer (PCS) logic. The PCS logic can be configured to support numerous industry-standard, high-speed serial data transfer protocols.
2009-03-13	Improved memory, cache boost DSP performance Texas Instruments has released the TMS320C6457 DSP at speeds of 1.2GHz and 1GHz, delivering up to 30 percent more performance at one-third less the cost of current single core DSPs.
2015-01-15	How to optimise floating point calculations on FPGAs Read about a methodology that provides designers a reliable technique for the baseline comparison of the peak floating-point computing capabilities of devices with very different architectures.
2014-10-16	How to improve FPGA comms interface clock jitters Know how external phase locked loops can be used to resolve problems faced when dealing with clock jitter in FPGA-based high-speed communications interfaces such as SerDes.
2008-02-28	Functional interconnect chips cut development time, costs IDT has launched a new family of CPRI-based functional interconnect chips that promise to reduce development time and cost, in part by offloading the translation and connection tasks from the current alternatives.