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2000-08-31 Scan path insertion and automatic test pattern generation
This application note describes the full Scan Insertion and the Automatic Test Pattern Generation (ATPG) flow supported by Atmel. It contains specific design guidelines for circuits that are suitable for scan path insertion and ATPG.
2000-08-29 Scan insertion and ATPG development via Synopsys test compiler
This application note presents Atmel's design guidelines, and then gives specific recommendations for scan insertion and ATPG vector generation using the Synopsys Test Compiler, version 3.2a.
2004-12-01 Scan design called portal for hackers
Any chip that uses scan designand any system built around it--may be vulnerable to hackers
2004-05-25 STATS expands turnkey solutions with DFT capabilities
STATS has expanded its integrated turnkey solutions with DFT capabilities that will assist customers in improving testability and throughput of their devices.
2002-09-10 Acromag acquisition boards have "mailbox" memories
The APC330 PCI and AcPC330 CompactPCI analog input boards from Acromag Inc. employ 16-bit ADCs that are able to scan channels in just 85s to achieve throughput rate of 125kHz
2003-07-10 Taiwan-based IC designer adopts Verplex tool
FMC SOTA Design Technology, a Taiwan-based design services company, has adopted Verplex Systems' formal verification software.
2002-10-09 Lightspeed boosts ASIC platform with 0.135m move
Lightspeed Semiconductor Inc. has given its modular-array ASIC platform a performance boost by sprucing up its architecture and shifting to 0.135m design rules.
2007-10-26 India researchers push new design methodology
Researchers from the Indian Institute of Technology together with another institute in Kolkata have proposed a layout-aware, coverage-driven methodology for ILS used to cut test application time and test data volume in high-density circuits.
2003-08-01 Design-for-test moves up to RT level
SynTest Technologies propelled its entire DFT flow up to the RTL with DFT-Pro Plus, thereby lessening the likelihood of errors.
2002-10-24 ASIC startup rethinks coarse-grained architectures
Fabless startup Telairity Semiconductor Inc. has joined the growing list of vendors offering some form of coarse-grained ASIC architecture, but with a significant twist.
2012-02-03 Advances in 3D-IC testing
Read about the design-for-3D-test architecture and implementation flow developed by researchers at Industrial Technology Research Institute based on the Synopsys test solution.
2006-10-16 Achieve low-power design success at 65nm
Tom Chau and Cheng Shi compile tips for designers to ensure success for advanced low-power designs at 90nm and 65nm.
2013-06-27 Understanding deep packet inspection (Part 2)
Learn about several architectures and building blocks that ease the creation of scalable, reliable DPI.
2008-03-18 Synopsys, SMIC tip 90nm reference design flow
Synopsys Inc. and SMIC have released an enhanced 90nm hierarchical, multivoltage RTL-to-GDSII reference design flow that benefits from advanced synthesis, design-for-test and DFM capabilities.
2006-07-20 Speedy JTAG controller priced below $10,000
The PCIe-1149.1 from Corelis is a single-lane PCIe card that is compatible with all compliant PCIe slots, whether they're x1, x4, x8 or x16.
2002-05-14 SoC test reels out of control
System-level IC testing, already complicated by increasing chip capacity and the growing use of third-party intellectual property (IP), is now being threatened from another quarter.
2010-11-03 Ricoh licenses DeFacTo's DFT solution
Ricoh Company Ltd announced the licensing of the HiDFT-Signoff Design-for-Test solution of DeFacTo Technologies SA.
2013-01-25 Reduce power estimation time from weeks to hours
Find out how to automatically generate a chip design's gate-level waveform from the RTL design environment without having to bring up the gate-level environment.
2005-06-16 Platform SoCs now possible
To a large extent, platform SoCs have been science fiction--until now. Such designs can span a wide range of markets.
2013-05-23 Performing synthesis-aware clock analysis
Read about a tool that performs clock structure analysis by tracing complex clock nets and visually presenting them to designers.
2004-10-29 Magma, LogicVision deliver integrated RTL-to-GDSII flow
Magma Design Automation Inc. and LogicVision Inc. have reached an agreement under which the companies will deliver complete interoperability between LogicVision's icBIST and Magma's Blast Create and Blast Fusion products.
2015-10-15 Logic analyser supports up to 4Gb/s debugging data rates
Keysight unveiled a logic analyser module that claims to deliver the industry's highest-data-rate state mode, highest timing mode (10GHz) and deepest memory depth (up to 400MB).
2005-05-02 It's time to move DFT to a higher level
Today, the 'D' in DFT does not really stand for design. All too often, at the gate level, it stands for do-it-late.
2014-03-03 Intro to C-slow retiming, system hyper pipelining
Read about the potential of system hyper pipelining especially in the multi-core era.
2012-08-08 Grasping power awareness in RTL design analysis
Find out how formats such as CPF and UPF play a key role in capturing power intent for RTL design analysis and verification.
2013-12-30 Examining JESD204B converter protocol advances
JESD204 was originally rolled out several years ago, but it has undergone revisions that are making it a much more attractive and efficient converter interface.
2014-05-23 Enable accelerated SoC physical design at RTL
In this article, we provide a review of the essential points to consider in order to ensure a smooth transition between the logical and physical worlds.
2005-01-17 Embedded test speeds system verification
Reusing embedded test speeds up system verification and provides an additional return on the silicon investment.
2002-10-02 Choosing an IP core
IP cores allow design teams to rapidly create large SoC designs by integrating pre-made blocks that do not require any design work or verification.
2003-12-16 C-MEMS filter aims at monitoring
C-MEMS is an alternative approach to optical monitoring.
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