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2011-03-22 Analog Bits releases Serdes IP for next-gen displays
Designed for 3D TVs and next-gen displays, Analog Bits' Serdes IP can reduce area, cost and power consumption and enable OEMs to eliminate LVDS.
2002-10-24 Agilent quad serdes measures 19-by-19mm
Agilent Technologies' HDMP-2689 four-port serdes IC measures 19-by-19mm and is designed specifically for Fibre Channel SAN equipment use.
2004-12-06 Agilent proves 6.25Gbps serdes core in 90nm process
Agilent Technologies Inc. has announced that it has validated its third-generation SerDes core in a 90nm CMOS process technology, making it possible for OEMs to embed as many SerDes channels (each operating at up to 6.25Gbps) as needed onto a single ASIC chip.
2002-06-04 Agilent EoS mapper integrates serdes, CDR, framers
The HDMP-3002 Gigabit Ethernet over SONET (EoS) mapper IC from Agilent Technologies Inc. integrates a serdes, CDR, and OC-3 to OC-48 framers, all required to efficiently format data for SONET/SDH networks.
2004-08-04 Agilent embedded SerDes ASIC sets performance record
Agilent Technologies Inc.'s embedded SerDes ASIC technology has set a performance record for storage and networking applications.
2002-02-05 Agilent CMOS chip integrates 36 serdes channels
2002-06-20 Agere serdes macrocell reduces power consumption
2005-01-07 Agere serdes core rolls for 90nm ASICs
Agere Systems is offering a serdes core for 90nm ASIC processes that's appropriate for several serial-interface standards.
2003-02-06 Agere licenses Accelerant's 6.25Gbps serdes
Agere Systems has taken an exclusive license to the 6.25Gbps serdes of Accelerant Networks.
2009-06-02 Advantages of AC-coupling in Serdes applications
This application note presents several benefits of using capacitors to AC-couple an LVDS data link. The article guides the reader through proper capacitor selection and termination topology. Common troubleshooting issues are discussed.
2011-11-17 Address challenges in 40G/100G SerDes design, implementation
Read about the various aspects of SerDes design such as transmit/receive portions.
2007-12-17 A fresh approach to Serdes I/O modeling
This paper will discuss need for algorithmic models, the interoperability problem, the need for IBIS BIRD 104 and the benefits systems companies and Serdes IP companies will derive from this new approach.
2010-02-22 40nm CMOS Serdes achieves 25Gbit/s
Avago Technologies has achieved serial 25Gbit/s Serdes performance in 40nm CMOS technology.
2007-06-22 3Gbps Serdes touts lowest output jitter of 50ps
National Semiconductor has introduced a 3Gbps multirate SDI Serdes that achieves the industry's lowest output jitter SDI serialiser (50ps) and highest input jitter tolerance deserialiser (0.6 units interval).
2008-09-02 30Gbit/s Serdes with clock jitter cleaner debuts from TI
Texas Instruments introduced a four-channel Serdes IC that enables high-speed, bidirectional, point-to-point data transmission with up to 30Gbit/s.
2006-08-28 ?SerDes upgrade offers more ESD protection
Using the same footprint and base architecture as its predecessor, Fairchild's new ?SerDes device promises enhanced ESD protection and reduced EMI.
2003-05-15 Xilinx ships 10Gbps CMOS transceiver family
Xilinx Inc.'s RocketPHY family of PHY transceivers is claimed as the first programmable logic system that delivers CMOS solutions at 10Gbps.
2003-03-12 Vativ rolls out transceivers, eyes interconnects
Vativ Technologies is sampling the first member of a planned family of transceivers for copper-based networks operating at 2.5Gbps and above.
2011-03-29 Using TLK2711-SP with minimal protocol
The TLK2711-SP is a 1.6-Gbps to 2.5-Gbps Class V SERDES transceiver capable of approximately 1.28-Gbps to 2-Gbps of data payload.
2003-12-16 Using ISSP technology in structured ASIC design
NEC's ISSP technology for designing structured ASIC has become popular with design engineers because of its easy-to-use design flow and clear road map for 90nm.
2003-03-17 Using FPGAs for high-speed serial interface design
FPGA provides the bandwidth and flexibility for industry leading high-speed interfaces. Its True-LVDS technology was designed to support the strict timing requirement of up to four high-speed differential I/O protocols.
2004-09-01 Understanding passive channel
It is imperative that engineers fully understand passive channel to tackle serial data transmission for 10Gbps and beyond.
2008-04-15 Tx/Rx chips support 3Gbit/s for SDI apps
Gennum has developed what it says is the industry's first single-chip transmit and receive products to support 3Gbit/s, as well as HD and SD, for SDI applications.
2007-01-31 Tundra division rolls out Interlaken IP core
Silicon Logic Engineering, a division of Tundra Semiconductor Corp., has announced the development of a licensable Interlaken protocol IP core for use in ASIC or FPGA designs.
2012-02-02 TI, Avago push signal data rates to the limit
Both companies are using the latest process technologies and signal integrity techniques to hit new milestones catering to responding to the need to carry ever more data over networks while keeping a lid on power and cost.
2015-05-08 The MCU guy's guide to FPGAs: The software
Embedded design engineers usually come from MCU background, so they often have only a vague idea as to what an FPGA is. In this article, we are going to consider the FPGA equivalent to MCU software.
2015-05-07 The MCU guy's guide to FPGAs: The hardware
Embedded design engineers usually come from MCU background, so they often have only a vague idea as to what an FPGA is. In this article, we'll consider the hardware aspects of the FPGA universe.
2003-03-28 TeraChip 160Gbps switch fabric consumes 15W
TeraChip Inc. has introduced the TCF16X10 single-chip, cell-switching fabric that is capable of switching 160Gbps while consuming 15W.
2009-06-01 Skew margin measurement for 4-Channel (3 data channels plus clock channel) LVDS serializers/deserializers
This application note shows a step-by-step method for measuring skew margin. Following this approach, you can clarify the specification and definition of skew margin in the data sheets for these 4-channel Serdes devices
2008-09-30 Simulator ensures better mixed-signal circuits
Infinisim has released Raser, a simulator, which is specifically designed for mixed-signal ICs.
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