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2002-10-03 SEMI's Oasis provides respite from GDSII
SEMI has rolled out the Open Artwork System Interchange Standard as a replacement for the GDSII file format, and said it promises a tenfold reduction in design data compared to GDSII.
2011-11-09 Sematech starts 3D tech forum
Sematech has launched an online forum to promote the development of standards for heterogeneous 3D integration.
2010-06-07 Scaling custom digital layout for next-generation chip design
This article details how one digital IC design team at a large fabless semiconductor company in the consumer product market is leveraging standards-based tool interoperability to maintain the benefits of hand layout for large, performance-sensitive 40nm designs.
2008-02-26 Rhines on EDA: End 'endless verification'
Walden Rhines of Mentor Graphics calls for a combination of formal methods, TLM techniques and intelligent testbenches to lower the cost of design verification.
2009-07-28 Power to take center stage at DAC
Power, arguably today's No. 1 headache for designers, will be the theme of workshops, tutorials, meetings, presentations and technical tracks at the 46th Design Automation Conference (DAC).
2006-10-16 Power standard standoff reaches stalemate
Participants behind two rival efforts to define a standard IC power description format are attempting to make their initiatives more inclusive.
2008-05-05 Power Forward Initiative gets MindTree onboard
MindTree has joined the Power Forward Initiative and will be offering a Common Power Format-enabled low-power flow to its design services customers.
2005-01-03 OpenAccess adoption challenging, worth it
Adopting OpenAccess database brings benefits to chip designers, but it's a challenging task that should not be taken lightly.
2007-05-09 Open constraint format sparks new EDA standards discussion
Is a new EDA standard effort in the offing? The recent Synopsys Interoperability Forum may have offered the public the first view of an open analog constraint format.
2007-05-16 Low-power IC design kit enables representative design
The Low-Power Methodology Kit from Cadence Design Systems includes a wireless "representative design" implemented using multiple supply voltage and power shutoff methods.
2011-12-21 JEDEC to release 3D IC standard
JEDEC will release in late December or early January 2012 the first 3D IC interface standard.
2006-10-04 Industry players meet to discuss standard for Open DFM
Participants of the Open DFM Model Workshop last week explored issues ranging from DFM flows to encryption and identified possible next steps.
2007-03-23 Hope fades for IC power standards union
The hoped-for-convergence between two rival IC low-power specifications will not likely take place anytime soon.
2007-05-01 Hope dims for power spec merger
Two rival specification formats for low-power IC design are now publicly available, and backers of both agree that it would be technically feasible to converge them into a single standard. But disagreements over how that convergence should take place threaten to block further progress.
2012-08-08 Grasping power awareness in RTL design analysis
Find out how formats such as CPF and UPF play a key role in capturing power intent for RTL design analysis and verification.
2008-05-30 Faraday, NemoChips develop low power mobile platform
Faraday Technology Corp. and NemoChip have partnered to develop next-generation low power mobile platform based on Cadence Low-Power Solution.
2012-10-19 Employ hierarchical methods for power intent specification
Here's a guide to using a hierarchical low-power design methodology.
2013-04-08 Electro-static discharge design best practices released
Silicon Integration Initiative said the document provides comprehensive guidelines for incorporating ESD protection into IC design flows.
2006-12-01 EDA vendor rivalry bogs single power spec
Amid calls for a single power spec throughout the design flow, EDA vendor rivalry continues to fuel two separate efforts to develop a low-power description standard.
2003-02-13 EDA users, vendors speak out for OpenAccess
The technical and business imperatives for the OpenAccess database and API were made clear by speakers and panelists at the second annual OpenAccess Conference in San Jose, California.
2006-09-18 EDA rivals spar over power issues
Any EDA vendor or large EDA user will tell you there's a compelling need for a standard way to express power-management intent throughout the IC design flow. The problem is that two separate groups are working toward that objective, amid profound disagreements over how to get there.
2006-11-14 EDA panelists call for standardized process design kits
Standardization of foundry process design kits will provide major benefits for analog and custom IC designers, according to panelists at the Synopsys EDA Interoperability Developer's Forum.
2007-02-27 EDA 'troublemakers' debate at DVCon
Confronted with provocative questions, DVCon EDA vendor representatives debated topics such as low-power standards, Cadence Design Systems' Skill language, and outsourcing to India.
2004-12-08 Dataquest issues 2004 EDA market report
The lack of new 65nm and 45nm tools will slow revenue growth in 2004 and 2005 and the EDA industry will report $4.2 billion in revenue for 2004.
2007-03-16 CPF-compliant tools aim for low power
Cadence Design Systems Inc. has added the Common Power Format to its existing logic design, verification and implementation tools.
2002-01-13 Coalition offers OpenAccess source code
Marking a major milestone for EDA tool interoperability, the OpenAccess Coalition has announced the availability of source code for the OpenAccess 2.0 database.
2014-12-29 CMC expands Spice model standards for SOI
Additional models called BSIM-IMG and HiSIM-SOTB were developed for extremely thin-body SOI CMOS (ETSOI) and will enhance the popular BSIM and HiSIM standards platforms.
2006-11-01 Cadence launches enhanced Virtuoso
Cadence Design Systems introduces a new version of its Virtuoso custom design platform. The release offers a constraint-driven design flow and is built on top of the OpenAccess database.
2005-03-28 Cadence contribution to Accellera standardize IC design kits
Cadence Design Systems Inc. has contributed its custom-design schematic symbol set to the OpenKit Initiative.
2006-07-11 Aprio, Pyxis collaborate on lithography-aware DFM router
Aprio and Pyxis announced the integration of Aprio's Halo-Quest and associated DFM View into the DFM-routing technology from Pyxis.
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