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2007-03-09 Fujitsu standardizes on Synopsys solutions for 65nm sign-off
Synopsys Inc. announced that Fujitsu Ltd has standardized on Synopsys' PrimeTime and Star-RCXT products as the timing sign-off solution for its 65nm ASIC and COT design flows.
2009-02-03 Synopsys, ST team up on SI sign-off tools
Synopsys Inc. and STMicroelectronics have agreed to join forces to accelerate the development of methodologies and flows for low-power and high-performance SoC timing sign-off to reliably unleash the full performance potential of advanced technology nodes
2004-06-17 Synopsys low-power solution supports 90nm designs
During the DAC 2004, Synopsys announced that its Galaxy Power offers the industry's first comprehensive low-power solution for today's advanced, high-performance 90nm designs
2002-05-08 SuperH picks Avant! design solution for latest MPUs
SuperH Inc. has selected Avant! Corp.'s SinglePass-SoC design solution to implement its latest microprocessor core, the SH-5
2005-05-11 Power network sign-off bridges transistor, gate levels
Claiming a new "hybrid" capability for voltage drop and electromigration sign-off, Synopsys will announce PrimeRail, a combination static and dynamic IC analysis tool that spans the transistor and gate levels
2014-12-11 LPDDR4 verification IP speeds up verification sign-off
The LPDDR4 VIP from Synopsys, based on a 100 per cent native SystemVerilog UVM architecture, aims to enable ease of use, integration and performance with regard to high-performance, low-power designs.
2006-01-24 EDA partnership yields DFM sign-off tool
Nannor Technologies Inc. and Predictions Software announced the integration of the Acuma chip level layout optimization tool and the EYES yield analysis software.
2002-05-14 Bay Microsystems delivers processors using Avant! EDA solution
Bay Microsystems Inc. has commenced delivery of its 10Gbps Montego internetworking processors, which employ Avant!'s SinglePass-SoC design automation solution
2007-11-09 Synopsys, UMC co-develop 65nm reference flow
Synopsys and UMC have co-developed a 65nm hierarchical, multivoltage RTL-to-GDSII reference design flow.
2010-06-22 Silicon-validated library tailored for 28nm designs
GlobalFoundries rolls a silicon-validated solution to help customers accelerate time-to-volume for complex SoC designs at 28nm and beyond
2014-11-11 Shifting to requirements-driven verification, test
Here is an evaluation of the pros, cons and potential obstacles to requirements-driven verification and test so you may decide if it is the next step in evolution.
2013-12-03 RTL signoff: A design imperative
"RTL Signoff" as an established concept has gained significance in the last year. However, writes Atrenta's Piyush Sancheti, does a commonly accepted definition of RTL signoff exist?
2007-09-04 Qualcomm joins IMEC's 45nm design program
Qualcomm has joined IMEC's technology-aware program and will be collaborating with the research institute on design methodologies for sub-45nm scaling challenges.
2013-06-06 Parasitic extraction in the double-patterning age
Determining the impact of double-patterning on electrical sign-off can be better achieved by understanding how PEX tools have evolved to handle this challenge
2007-10-29 ATPG offers improved low power management
Synopsys has expanded the low power management capabilities in its Galaxy test solution reduce the time and effort needed to generate high-quality, power-aware manufacturing tests for ICs
2006-11-16 Valor eases design with collaborative tool
vShare will provide a centralized, scalable platform with secure access to DFM-related design information, including design reviews, design changes and manufacturing sign-off
2006-08-30 Toshiba tapeouts 90nm IC with Synopsys compiler
Synopsys announced that Toshiba has used the Synopsys IC Compiler physical implementation solution to tape out its next-generation TC90515XBG home digital network chip
2004-12-03 Synopsys' Galaxy platform supports Sasken reference flow
Synopsys Inc. has announced that Sasken, an embedded telecommunications technology solution provider, has used its' Galaxy design platform to develop a reference flow to enhance the implementation and signoff process for its complex designs
2005-03-17 Synopsys unveils 'next-gen' compiler for physical design
Synopsys unveiled a physical design solution, which the company claims provides leading-edge performance and already carries endorsements by key IC suppliers
2005-04-18 Synopsys unveils 'next-gen' compiler
The company introduces a physical design solution which it says provides concurrent clock tree synthesis, routing and yield optimization
2008-03-17 Succeed at 65nm design
A true DFM-aware environment accounts for process variability and lithographic effects in the context of timing, power, noise and yield at every stage of the flow. This begins with the characterization of the cell library, continues through implementation, analysis and optimization, and ends with sign-off verification
2005-10-07 New design flow for ARM Cortex-A8 processor from Synopsys
Synopsys and ARM demonstrated the successful integration of Synopsys' Galaxy RTL synthesis, hierarchical design planning, physical implementation solution, sign-off and Discovery verification solution within a high-performance design flow for the new ARM Cortex-A8 processor.
2005-09-26 Forte upgrades Cynthesizer
Forte Design Systems announced that it has upgraded its Cynthesizer behavioral synthesis solution to provide a more extensive production ESL design flow
2010-05-14 ESD physical integrity tool enables early prototyping
The PathFinder ESD integrity solution aims to enable designers to perform early prototyping, circuit optimization and full-chip signoff
2012-04-30 Design for power methodology: From architectural plan to signoff
Here's a look at a holistic design for power methodology that spans from architectural decisions through front-end design to physical implementation and sign-off
2006-04-06 Hisilicon adopts Synopsys' Galaxy design platform
Synopsys announced that Hisilicon Technologies has adopted Synopsys' Galaxy Design Platform as its primary IC design flow for 130nm designs.
2004-12-17 Winbond achieves silicon success with Synopsys design platform
Winbond Corp. has achieved first-pass silicon success using Synopsys Inc.'s Galaxy Design platform for its latest 130nm, MPEG-4 multimedia chips.
2012-11-16 Virtual prototype for Android HW-SW dev't (Part 1)
Know how to do full software integration of handset hardware in the context of the Android software platform.
2013-07-18 UMC adopts Cadence's DFM flows for 28nm node
The flows address both random and systematic yield issues and incorporate DFM prevention, analysis, and signoff capabilities.
2007-12-14 TSMC, Altera, Synopsys collaborate on 45nm extraction tool
Synopsys has announced the qualification and immediate availability of the Synopsys Star-RCXT parasitic extraction tool for TSMC's 45nm process technology.
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