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What is analogue simulation?
Modelling or simulation of an electronic circuit using representations of the actual circuit voltages, currents, and component values instead of simplified digital state representations.
total search2143 articles
2014-04-09 1nm InN wires efficiently convert energy into light
Researchers at the NERSC revealed that indium nitride will emit green light if scaled to a nanometre-wide wire, and can then be modified to emit different colours by varying the wire sizes.
2005-02-01 10x 'fast SPICE' speedup promised
Nascentric vows to fill the gap in the 'fast SPICE' market left by Nassda acquisition.
2009-04-20 0.18?m RFCMOS design kit helps trim die size
China foundry Grace Semiconductor Manufacturing Corp. has released its advanced 0.18?m RFCMOS process design kit (PDK) through an exclusive collaboration with Sentinel IC Technologies.
2004-05-18 0-In tool verifies metastability effects
Claiming a "breakthrough" solution for the automatic verification of metastability effects, 0-In Design Automation is preparing Archer CDC-FX, an addition to its clock-domain crossing (CDC) verification tool.
2003-04-04 0-In releases monitor for PCI Express
0-In Design Automation has released a new CheckerWare Monitor for the PCI Express standard.
2003-01-31 0-In pumps up assertion-based verification suite
Armed with two new products and new technology, 0-In Design Automation is rolling out version 2.0 of its assertion-based verification suite.
2004-01-01 0-In assertion compiler is multilingual
0-In Design Automation announced a compiler that reads assertions in multiple formats and outputs synthesizable Verilog.
2003-11-13 0-In assertion compiler has multilingual features
The company will announce an enhanced assertion compiler for its Assertion-Based Verification (ABV) tool suite.
2002-10-01 'Religious' wars abound
Should resets be synchronous or asynchronous? Should synthesis handle buffer insertion? Should OpenVera assertions be added to System Verilog? All these questions have provoked controversies in recent weeks, the first two in E-Mail Synopsys Users' Group (ESNUG) postings and at our EEdesign site.
2008-04-01 'Openness' fulfills SystemVerilog promise
Notes Stan Krolikoski of Cadence Design Systems: Open Verification Methodology is a truly open SystemVerilog class library and methodology package that can be used free of any restraints imposed by either Cadence or Mentor.
2008-01-21 'Open' is (not) just a four-letter word
There is presently a measure of "openness fatigue" permeating the industry, but that's because the term "open" has been far too often applied to products and organizations that are far from open in significant ways.
2006-08-07 'First' FPGA-based development kit rolls for PXIe
Claiming an industry first, PLDA recently said it is launching the PXIe XpressLite CY2 Development Kit for CompactPCI Express.
2006-11-16 'DFM too complex,' experts say
Speakers told the Bacus Photomask Technology Symposium that DFM technology is too complex and suggested the use of standardized layout elements, library cells or an "integrated" DFM methodology.
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