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2002-05-02 Virage offers multiport memory for SoC designs
Memory designer Virage Logic Corp. intends to market a configurable SRAM-based multiport memory that can perform three R/W operations simultaneously, increasing data throughput in today's embedded systems and meeting the expected demands of parallel or pipelined processors in future SoC designs.
2002-05-24 VIA adopts Avant! Star-SimXT for SoC design verification
VIA Technologies Inc., a developer of PC core logic chipsets, microprocessors, multimedia and communications chips, has selected Avant! Corp.'s Star-SimXT simulator for sign-off verification of its SoC designs.
2005-09-09 Verisilicon to offer ZSP400-based SoC solutions
Fabless ASIC design foundry VeriSilicon Holdings Co. Ltd has licensed LSI Logic Corp.'s ZSP400 DSP core to strengthen its IP portfolio.
2014-12-17 Verifying multi-processor SoC cache coherency
Learn about a highly automated approach to cache coherency verification at the SoC level: generation of test cases to stress every aspect of a multi-processor, multi-memory, multi-level cache design
2002-02-20 VCX, Chartered team to streamline mixed-signal SoC design process
Silicon foundry Chartered Semiconductor Mfg and Virtual Component Exchange have entered into an agreement that designates Chartered as a preferred mixed-signal foundry for VCX partners.
2013-06-25 Utilising non-volatile memory IP in SoC designs
Integrating anti-fuse NVM on chip for program storage results to increased margin as well as independence from vagaries of supply chain and component availability.
2007-06-07 USB PHY trims power in 65nm, 45nm SoC designs
Chipidea introduces a USB PHY core for 1.8V I/O devices that it says offers the industry's lowest power consumption for SoC designs in the 65nm and 45nm advanced technology nodes.
2004-05-03 Toshiba used Synopsys platform for SoC designs
Synopsys has announced that Toshiba has taped out multiple 90nm SoC designs for its audiovisual and office equipment product lines using Synopsys' platform.
2006-04-17 The case for real-time visibility in SoC designs
Visibility into an SoC requires a mix of hardware and software mechanisms to collect data within the chip itself
1999-09-09 System verification: Essential for digital wireless system-on-chip (SoC) designs
This paper discusses verification and hardware/software co-verification in SoC applications. It also deals with the SoC verification issue, and not the details of designing 3G wireless applications
2004-06-15 Synopsys IC, SoC tool reduces design time, cost
The new coreAssembler from Synopsys can be used to implement an IP based flow that can reduce design time, risk and cost of advanced SoC platforms and ICs
2005-04-29 Synopsys DesignWare supports GUC SoC designs
Synopsys Inc.'s DesignWare intellectual property (IP) has been chosen by design foundry Global UniChip (GUC) for use in complex system-on-chip (SoC) designs.
2000-12-01 SuperHyway provides SoC backbone
A step ahead of CompactPCI, Compact Packet Switching Backplane (cPSB) is emerging as a viable solution for interconnect problems.
2013-10-22 Structural, reset faults in SoC designs (Part 2)
Know some of the basic structural issues in reset architectures used in advanced nanometre scale SoC designs.
2013-10-16 Structural, reset faults in SoC designs (Part 1)
Here's a two-part survey of some of the basic structural issues in reset architectures used in advanced nanometre scale SoC designs.
2010-01-22 Solving today's problem of SoC verification
As more complex, mixed-signal SoC designs continue to stress verification methodologies and schedules, designers need new approaches in solving today's test challenges. Mixed-signal verification presents a unique challenge as the analog portion of the design requires highly accurate and time-consuming, analog simulation.
2013-02-06 Solving SoC and FPGA prototyping debug issues
Read about the accelerated development, verification and debugging of ASIC hardware and software.
2013-06-24 Software burden for 28nm SoC dev't doubled over 40nm
The software cost for developing 28nm SoCs more than doubled from the previous node, according to Semico Research.
2002-07-17 SOCLE Technology launches latest SoC platform
SOCLE Technology Corp. has introduced its latest SoC-ImP pre-verified SoC design implementation and ?Platform
2002-11-18 SoC/IP designs need next-gen solutions for integration verification
As the cost of SoC design plus time-to-wolume pressure continue to rise, a next-generation simulator for SoC integration verification is required to ensure functionality
2014-01-05 SoC implementation with dependable 50% duty cycles
Here's a new approach to implementing clock dividers in a system-on-chip design that supports both high performance and low power.
2008-04-21 SoC complexity, cost compel companies to collaborate
Growing complexity and the staggering costs associated with designing SoCs are forcing companies to seek collaboration on a variety of IP issues.
2002-02-16 SoC complexity demands new test strategies
This technical news article describes an overview of how with the complexity of new methods in testing and verifying SoC designs, engineers should learn to tweak their strategies to accommodate a more versatile SoC production run.
2006-06-02 SMIC adopts ARM physical IP for designs at 90nm
SMIC and ARM jointly announced that SMIC has adopted the ARM Metro and Advantage products.
2010-06-22 Silicon-validated library tailored for 28nm designs
GlobalFoundries rolls a silicon-validated solution to help customers accelerate time-to-volume for complex SoC designs at 28nm and beyond.
2006-03-07 Sequence addresses needs of SoC designs below 90nm
Sequence Design announced the next generation of its PowerTheater design suite to meet the demanding requirements for wireless, mobile and large SoC designs below 90nm.
2003-03-03 Selecting a CPU core for multi-CPU SoC designs
This article examines the many features of processor cores being considered for multi-CPU designs
2012-02-10 Samsung, Cadence partner in nanometer SoC design
The companies will collaborate on a design-for-manufacturing (DFM) infrastructure to tackle physical signoff and electrical variability optimization for 32, 28 and 20nm ICs.
2014-11-18 Reducing SoC power: Where should the focus be
Typically, efforts to manage power consumption in SoC design are focused on the CPU and GPU. The SoC interconnect is one area that needs to be re-evaluated
2013-07-30 Reduce SoC power use without high-level EDA tools
Read about several situations where high level design tools are not useful and are sometimes a hindrance.
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