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2008-03-17 Succeed at 65nm design
A true DFM-aware environment accounts for process variability and lithographic effects in the context of timing, power, noise and yield at every stage of the flow. This begins with the characterization of the cell library, continues through implementation, analysis and optimization, and ends with sign-off verification.
2003-07-01 Structured ASICs rescue endangered species
Structured ASICs can help the ASIC industry as it struggles against FPGAs and unreachable mask costs.
2005-11-11 Structured ASIC devices embed PCI Express physical layer
ChipX has introduced a new structured ASIC family that it claims is a low-risk alternative to traditional ASIC and FPGA devices
2006-06-12 Structured ASIC development kit with PCIe PHY
ChipX's development kit for the CX6100 structured ASICs integrates the same PCIe PHY used in ChipX's CX6100 structured ASIC family with a PCIe development board and FPGA.
2011-06-07 STMicroelectronics completes 20nm chip tapeout
The tapeout of STMicroelectronics' first 20nm technology demonstrator test chip has been successfully completed with Synopsys.
2004-12-21 STMicro has full 65nm IC, offers 65nm design platform
STMicroelectronics said Dec. 16 that it has completed the design, and tape-out, of a complex IC that demonstrates its 65nm manufacturing process technology.
2002-09-01 Startups with new ideas
In spite of industry consolidation and slowing growth rates, EDA startups are bringing new ideas and technology to chip designers.
2006-10-16 Startups take on analog design automation
Automating analog IC design has proven to be a tough challenge, but two EDA startups are promising to do just that with a new "analog synthesis" technology.
2007-02-01 Startup weaves new foundation for chip design
Fabbrix claims it can provide the regular circuit patterns or 'fabrics' needed by manufacturable designs at 65nm and belowwithout area, performance or power penalties.
2002-05-02 Startup promises automated cell optimization
Electronic design automation startup Zenasis Technologies Inc. wants to bring the precision of full-custom design to ASIC and system-on-chip design with a cell-optimization technology it plans to release sometime next year.
2004-12-22 ST unveils 65nm CMOS design platform
ST's 65nm CMOS design platform will allow designers and customers to start developing next-gen SoCs for low-power, wireless, networking and consumer apps.
2006-04-19 Socle SoC platform validated on UMC's 90nm process
Socle Technology and UMC announced that Socle has validated in silicon its ARM926EJ-based SoC platform.
2011-01-20 SoC design solution optimized for HKMG tech
Synopsys Inc. announced that it is delivering a low-power, high-performance SoC design solution optimized for the Common Platform alliance (CPA) 28nm high-k metal gate (HKMG) technology.
2007-08-15 SoC controller targets space applications
Tower Semiconductor Ltd and Ramon Chips Ltd have completed a prototype radiation-hardened SoC controller for space applications.
2002-08-26 SMIC launches 8-inch wafers using 0.185m process
Semiconductor Mfg Int. Corp. has commenced production of its 8-inch wafers using 0.185m process.
2003-10-14 SMIC adopts design platform by VeriSilicon
VeriSilicon Inc. has released its Standard Design Platform for Semiconductor Mfg Int. Corp.'s 0.15&181;m generic and low-voltage CMOS process technologies.
2006-06-02 SMIC adopts ARM physical IP for designs at 90nm
SMIC and ARM jointly announced that SMIC has adopted the ARM Metro and Advantage products.
2014-02-17 Smart TV SoC supports 4K content
Realtek teamed up with UMC and Synopsys to design a smart TV SoC in the 40nm process that addresses the issue of large pixels found in super-sized displays.
2001-06-01 Single-mask simplicity needed for SoC
The move to multimillion-gate chips made it necessary to adopt design-reuse strategies for new SoC devices.
2002-08-14 Silicon Metrics tool designs, models I/O
Silicon Metrics Corp. has released a tool that helps characterize, model, and verify the electrical spec compliance of a design's I/O.
2012-03-06 SIA to still focus on data programs
SIA president, Brian Toohey, is hopeful that solutions could be found that would enable SIA to continue reporting accurate data on microprocessor sales pooled by WSTS in a way that Intel and AMD would be comfortable with.
2005-10-21 Satellite-to-cellphone service test called successful
Suitcase-sized satellite phones may make way for standard cellphone handsets, according to Mobile Satellite Ventures (MSV), which said Wednesday it has successfully tested a satellite link to a standard CDMA cell phone.
2008-05-09 Run practical power network synthesis
Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are commonly designed as custom switch cells of fixed sizes. The method described in this article avoids this unrealistic assumption and introduces the concept of a "fake via" to enable power network synthesis using existing EDA tools.
2002-11-26 Risks of customer-owned tooling send designers to ASICs
Like do-it-yourselfers who wished they had called the plumber or electrician instead of botching a home repair, chip makers seem to be having second thoughts about customer-owned tooling.
2013-10-02 Researchers demonstrate carbon nanotube powered computer
Stanford researchers hope to revitalise carbon-nanotube development efforts by surmounting its problems with a CMOS compatible process they call "imperfection-immune design".
2010-07-20 Renesas puts bid for world market in high gear
With its acquisition of Nokia's modem business, Renesas makes clear its intention to take the lead in the global mobile technology market.
2010-03-22 Reducing power consumption in MPUs with FPGAs
The newer and better FPGA technology brings with it a whole new set of challenges for the designer. Power utilization is one issue that moves to the forefront when designing an FPGA-based embedded system for a handheld or portable device.
2007-07-23 Reconfigurable logic IP rolls for 65nm, 45nm nodes
Lightspeed Logic tips a new generation of its Reconfigurable Logic IP for the 65nm and 45nm process nodes.
2006-06-16 Real-life power gates a bigger challenge
Power gating requires a system-level understanding of where to add power gates, and how and when to control them. A domain-aware infrastructure can help reduce overall turnaround time.
2007-05-28 Re-synthesis solution cuts 24% die area
California-based Nangate Inc. claims that its re-synthesis solution will provide digital IC designers with the advantages of full custom design implementation while preserving the benefits of cell-based design methodologies.
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