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2008-08-01 FPGAs are all set for next process nodes
Altera Corp. today is expected to become the first FPGA vendor to launch a family of 40nm FPGAs. In addition, Altera will announce the 40nm HardCopy IV structured ASICs, as well as corresponding software tools for both device types. The families promise to enable a new class of single-chip, multicore and related complex devices.
2005-03-24 Four industry players team up to address power issue
Members of the Silicon Design Chain Initiative announced silicon-validated, low-power design techniques that promise to achieve power savings of over 40 percent on a 90nm test design.
2002-12-27 Foundries wield intellectual property to gain an edge
Faced with excess manufacturing capacity and complex chip design challenges, Taiwan's biggest pure-play foundries are taking a fresh approach to the way they manage IP.
2004-06-10 Flextronics partners with Magma, eASIC
Flextronics Semiconductor has partnered with Magma Design Automation Inc. and eASIC Corp. to provide an optimal structured ASIC solution.
2005-12-22 Faraday tapes out ASIC production chips with Cadence platform
Cadence announced that Faraday has taped out ten 130nm ASIC production chips with the Cadence Encounter digital IC design platform.
2003-06-06 Faraday programmable cell array accelerates time-to-market
Faraday Technology has introduced its Three-Mask Programmable Cell Array family of high-performance, high-density and easy-to-use reconfigurable cell arrays.
2008-05-01 Fabless ASIC camp gets funds
eASIC Corp. has announced that it raised $48 million in late-stage financing, joining a number of other fabless ASIC vendors that have completed sizable funding rounds to boost their competitiveness.
2006-12-13 Fabbrix weaves 'fabric' for IC design
Fabbrix Inc., a startup that aims to reshape IC design through the use of regular design patterns or "fabrics," announced a collaboration with PDF Solutions Inc.
2001-06-01 Extraction method verifies IP functions
To keep in pace with silicon technology advancement, verification of the reused custom logic against its original counterpart should be considered as an integral part of the reuse process.
2008-04-25 Enhanced Cortex-M3 achieves ultralow power
The latest release of the Cortex-M3 processor by ARM includes a new controller that allows almost instantaneous return to fully active mode from an Ultra-Low Leakage retention state and introduces enhanced power management features.
2016-02-18 Energy harvesting calls for full-spectrum MCU efficiency
Energy harvesting is becoming a practical option for an increasingly wide range of sensor-oriented designs for the internet of things. Find out why.
2015-03-16 Embedded flash IP boosts power efficiency of IoT, wearables
Faraday Technology and UMC announced a complete set of low power consumption fundamental IPs developed for UMC's 55nm Low Power (LP) embedded flash process.
2004-03-08 Embedded 16-bit processor market to decline, analyst says
Global consumption of customer-specific, cell-based designs containing at least one 16-bit processor is expected to decrease from $374.9 million in 2003 to $363.5 million in 2008, according to market research firm In-Stat/MDR.
2015-04-24 EDA tool reduces design time for FinFETs
The Calibre xACT claims to quickly and accurately extract parasitic capacitance, resistance and inductance for IC designs including digital, custom, analogue and RF.
2007-02-16 EDA growth to continue this year
The EDA industry grew faster than expected in 2006 and is up for another good year, thanks to a healthy IC industry, an insatiable CE market and a move to 65nm and 45nm technologies.
2008-10-20 ECU and DSP function
This document describes the use of embedded computational units (ECUs) in QuickLogic FPGAs to implement DSP functions.
2007-01-31 Dongbu, ARM extend delivery of IP design for 130nm
Dongbu Electronics and ARM are joining efforts to extend the availability of ARM low-power and speed-and-density products to designers developing chips using Dongbu's CMOS process at the130nm node.
2011-12-08 Designing 3D-ICs (Part 2)
Here's the second instalment of this series that tackles the tools that can be used to handle a complete backend flow, and enable true 3D design partitioning, synthesis, placement, and routing.
2008-06-12 Design tools eye ARM core for various apps
Cyclos announced a proof-of-concept processor implementation using its platform and design flow. This can be used to achieve low-power, resonant-clock implementations of synchronous ASICs and SoCs without changes to their development and verification environments.
2009-10-06 D2S, Advantest partner on maskless SoCs
D2S unveils packed stencil technology that works with Advantest's e-beam direct write lithography equipment.
2007-11-01 Customizable MCUs take on FPGA tasks
Using a customizable MCU with an MPCF allows designers to integrate their custom IP into a near off-the-shelf solution. It offers the cost, power consumption and performance benefits of a full-custom ASIC, with NREs and design cycle that are not much different from those of an off-the-shelf MCU + FPGA design.
2002-05-17 Cray CMOS team receives funding for advanced ASICs
Wisconsin-based Silicon Logic Engineering has received $2.5 million in venture funding under that state's certified capital companies program.
2007-03-16 CPF-compliant tools aim for low power
Cadence Design Systems Inc. has added the Common Power Format to its existing logic design, verification and implementation tools.
2004-10-01 Costello decries lack of EDA vision
One of the more colorful figures in EDA history believes the design automation industry today is suffering from a lack of imagination.
2005-07-01 Cores ace networking benchmarks
Tensilica tops the Embedded Microprocessor Benchmark Consortium suites for network processors.
2006-11-16 Consider a structured-ASIC design methodology
Rob Schreck enumerates the do's and don'ts for using a structured-ASIC design methodology.
2013-05-06 Conquering FinFET challenges
Here's a look at the challenges from custom/analogue, digital, parasitic extraction and signoff perspectives.
2006-12-01 Configurable sections within an SoC
Regardless of the fabric used, designers should be aware of a few do's and don'ts when designing configurable sections within an SoC.
2007-05-01 Commoditization shakes ASIC business
The tumultuous ASIC business is undergoing a shakeout amid dwindling design starts and soaring technology costs.
2007-12-28 Commentary: A few fabless fables
As the fabless companies jostle and compete for market positioning and market share, they are subject to the larger trends that transact in the fabless supply-chain world.
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