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2002-05-30 TSMC adopts Cadence's signal analysis for reference design flow
Taiwan Semiconductor Mfg Co. has adopted Cadence Design System Inc.'s CeltIC signal-integrity analysis solution for its 0.135m reference design flow
2007-05-30 Timing analyzer vows dramatic speedup
Extreme DA is set to roll out GoldTime, a new multithreaded static and statistical timing analyzer that runs on multicore platforms
2005-08-16 Timing analyzer puts ASIC-like functionality in FPGAs
Actel Corp. rolls out a static timing analysis engine that brings ASIC functionality into the FPGA world.
2001-05-01 Timing analysis tools greatly impacts a successful design
Today, static timing analysis tools have matured to the point of handling significantly more complex design styles. This article examines the different kinds of timing analysis products used in ASIC, FPGA, and board-level design.
2005-03-03 Timing analysis needs overhaul, speaker says
New IC devices, circuits, and physical effects will drive a new generation of timing analysis tools, said David Hathaway, senior technical staff member for EDA at IBM Microelectronics, at a keynote speech at the Tau timing workshop here Monday (Feb. 28
2005-04-01 Statistical tool shift: It's all in the timing
Startup Extreme DA's mission is 'variation-aware' IC analysis. Can four guys in borrowed office space make a big impact on chip design
2006-08-16 Statistical timing revs for 45nm era
Statistical-timing analysis may represent the next major technology shift in nanometer IC implementation, but it's going nowhere fast without statistical-timing models
2004-06-15 Statistical timing can boost IC performance, panelists say
The performance of just about every digital IC design relies heavily on static timing analysis results.
2003-12-26 Statistical static timing analysis ensures IC performance
Static timing analysis is one of the pilings upon which the whole edifice of modern IC design has been erected.
2002-12-09 Researchers call for fundamental shift in timing analysis
Calling for a new approach to the design of digital circuits, researchers at the ACM/IEEE Tau workshop presented strong arguments for a move to statistical, or "probabilistic," timing analysis
2006-10-16 One timing tool serves 65nm, 45nm designs
Cadence Design Systems introduced the Encounter Timing System, described as a "signoff-quality" timing product for nanometer SoC design
2002-12-11 Nassda aims Critic timing technology at ASICs
Extending its fast circuit-simulation technology into digital design, Nassda Corp. has claimed a breakthrough with a transistor-level, full-chip, dynamic timing analyzer
2004-10-18 Growing challenges in nanometer timing analysis
By including nanometer effects, advanced timing analysis methods deliver the precision needed to accurately predict performance and avoid costly silicon iterations
2006-07-25 Fujitsu announces environment for statistical timing analysis
Fujitsu Microelectronics America announced that it is the first semiconductor supplier to provide a comprehensive environment for statistical timing analysis for ASIC and COT customers
2006-12-04 Clear Shape offers electrical DFM analysis solution
Clear Shape Technologies has announced OutPerform, said to be the first complete and silicon-correlated electrical DFM analysis and optimization product to enable designers using sub-90nm processes to control the impact of lithography, mask, etch, RET, OPC and CMP effects on their chip parameters
2003-05-08 Analysis tool combines dynamic, static timing methods
Nassda Corp.'s HANEX circuit-level timing and crosstalk analysis tool is targeted for use in digital designs of 130nm and below
2013-08-27 Achieve successful timing closure
Find out how to derive design margins for successful timing closure
2006-09-07 Signoff quality' timing tool rolls for 65/45nm designs
Cadence Design Systems introduced the Encounter Timing System, described as a "signoff-quality" timing product for nanometer SoC design
2004-04-23 Timing optimization rolls for logic designers
Silicon Dimensions has released an add-on to its Chip2Nite floor planner, block design and analysis offering
2008-01-29 Synopsys upgrades signal integrity analysis suite
Synopsys has announced that the 2007.12 release of its PrimeTime suite has set a new performance standard for both static timing and signal integrity analysis, accelerating turnaround time and design closure for today's nanometer designs.
2013-04-18 Symtavision touts SymTA/S with Ethernet timing analysis
The latest feature targets the automotive market and integrates with existing in-vehicle network timing analyses for CAN and FlexRay as well as with scheduling analysis for AUTOSAR-based ECUs
2013-02-27 Symtavision adds timing analysis, design support to SymTA/S 3.3
The suite claims to feature enhanced timing analyses including support for FlexRay System Distribution, CAN-FD standard, buffer fill level analysis for COM and gateways, and Gantt chart customisation
2015-01-19 RFID sniffer touts real-time analysis of reader, tag signals
The ultra-high frequency device from CISC Semiconductor records and analyses the communication between the tag and reader in real-time, and covers the RF band from 50MHz to 2.2GHz.
2012-11-09 Remove pessimism and optimism in timing analysis
Pessimism could not only increase the time to fix the critical paths, but could also adversely affect other crucial parameters such as power and area.
2004-05-11 Nassda adds hierarchical timing analysis
Nassda is preparing Hanex v5.0, an upgrade of its static and dynamic circuit simulator
2012-08-08 Grasping power awareness in RTL design analysis
Find out how formats such as CPF and UPF play a key role in capturing power intent for RTL design analysis and verification
2012-12-27 802.11ac power measurement and timing analysis
Learn how a peak power analyser supports the unique 802.11ac power amplifier design and validation test requirements.
2014-07-31 Timing IC integrates clock generators, jitter attenuators
The chips provide an I2C-configurable platform featuring a combination of frequency translation capabilities and
2010-05-28 Timing analyzer speeds up multicore designs
XMOS has released the XMOS Timing Analyzer (XTA) that accelerates the design of embedded applications using its family of XCore processor arrays
2013-05-23 Performing synthesis-aware clock analysis
Read about a tool that performs clock structure analysis by tracing complex clock nets and visually presenting them to designers
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