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2013-12-16	Imec unveils strained germanium FinFETs The device, fabricated with a Si Fin replacement process on 300mm Si wafers, shows a possible evolution of the FinFET/trigate architecture for 7nm and 5nm CMOS technologies.
2004-12-09	IBM describes strained germanium technique IBM Corp. on Monday (Dec. 6) claimed that it has demonstrated a strained germanium technology that triples the performance of a standard transistor used in semiconductors.
2005-09-27	Strained silicon to take IEDM spotlight With high-k dielectrics apparently delayed beyond the 45nm node, this year's International Electron Devices Meeting will focus on second-generation strained-silicon techniques as the main pathway to faster transistors
2005-09-29	Soitec, SEZ to speed industrialization of strained SOI substrates The Soitec Group and the SEZ Group have initiated a joint development program (JDP) intended to speed the industrialization of next-generation strained silicon-on-insulator (sSOI) substrates
2003-05-27	Soitec, ASM target strained silicon on SOI Soitec and ASM International announced that they are working together on strained SSOI technology, which targets the 65nm node
2002-04-10	Russian technology waves goodbye to strained silicon A Welsh start-up has linked with Russian technologists to develop a transistor architecture that could go against strained silicon as a way of boosting transistor performance without forcing the industry to move to much smaller devices
2002-08-15	Intel adopts strained silicon for 90nm process Intel Corp. said that it will add strained silicon technology to its 90nm technology mix, and will use the process to make the Pentium 4 microprocessor code-named "Prescott" starting next year
2003-10-02	High-k, strained Si leaving the lab With performance improvements getting harder to wring out of CMOS by transistor shrinks, researchers are increasingly turning to strained silicon, high-k oxides, and different types of on-chip silicon-crystal orientation
2005-04-14	Freescale, Soitec claim 45nm designs with strained SOI A collaborative effort between Freescale Semiconductor Inc. and Soitec Group has resulted in the ability to build 45nm CMOS devices using strained silicon-on-insulator (SOI) substrates, the companies claimed
2002-10-18	AmberWave cuts SiGe layer from strained-silicon process AmberWave Systems Corp. claims to have worked out a form of strained silicon that removes the SiGe layer and provides an ultrathin silicon top layer to build high-performance devices
2015-04-23	Analyst predicts Intel's 10nm plans According to a forecast by David Kanter, Intel will use quantum well FETs starting with its 10nm process that will use two new materials, InGaAs for n-type transistors and strained Ge for p-type devices
2002-12-12	Intel, IBM joust 90nm technology at IEDM meet Intel and IBM each came to the 2002 International Electron Devices Meeting claiming logic performance leadership at the 90nm.
2015-07-13	IBM surpasses Intel with 7nm node tech IBM Research claims to have perfected the extreme ultra-violet (EUV) lithography and using silicon-germanium channels for its finned field-effect transistors (FinFETs
2003-11-12	AmberWave obtains rights to Agere silicon patents AmberWave Systems has secured exclusive rights to sub-license nine key strained silicon patents from Agere Systems Inc
2013-06-14	Imec presents RRAM, FinFET innovations At this week's VLSI 2013 Technology Symposium, Imec presented improved quantitative statistical prediction of the RRAM operation as well as the the first strained germanium devices based on a Si-replacement process.
2003-12-03	Soitec upgrades equipment from SOI wafer production Soitec announced that it is expanding its manufacturing capabilities to ensure broad industrial availability of strained SOI wafers
2002-06-19	Materials transitions stalk CMOS scaling With the transition to copper and low-k interconnects showing just how difficult changes in materials can be, technologists gathered at the Symposium on VLSI Technology to consider a brace of materials challenges?ranging from new gate oxides to SOI and strained-silicon channels
2015-07-29	Extending Moore's Law: Progress underscores SiGE, nm-ICs Looking closer at the industry, much attention has been devoted to silicon-germanium (SiGe) heterojunction technology as the next step in building silicon-based ICs down below 10nm
2007-02-16	AMD bares first details of 45nm plan The company's 45nm blueprint includes the use of copper interconnects, porous low-k-dielectric films, embedded strained silicon and advanced annealing
2006-03-16	GaAs dielectric points past silicon Freescale Semiconductor's laboratory recently announced that it has cracked a 40-year-old puzzle—how to deposit a defect-free dielectric on GaAs.
2004-04-23	VLSI papers weigh 65nm, new circuits While technologists look to 65-nanometer nodes, circuit designers by and large are two generations back.
2002-04-15	TSMC exec advocates slower steps between process nodes Taiwan Semiconductor Mfg. Co. Ltd said it aims to deliver its first ICs based on 90nm design rules by the third quarter of this year, about one year ahead of the time frame cited in the industry's International Technology Roadmap for Semiconductors.
2004-06-18	TI outlines new options for chip scaling Texas Instruments Inc. (TI) revealed that its semiconductor research teams have developed cost effective techniques to lower chip power consumption, and a new approach to increase overall performance.
2006-06-02	Symposium to mull 45nm challenges Technologists attending the 2006 Symposium on VLSI Technology in mid-June will hear about multiple facets of 45nm processes
2013-11-28	Soitec, SunEdison sign patent license deal The agreement provides each company with access to the other's patent portfolio for SOI technologies and ends all outstanding legal disputes between the companies.
2003-11-26	Soitec, KLA-Tencor team to enhance SOI wafer technology Soitec and KLA-Tencor have announced a joint program aimed to improve the quality and cost of production of SOI wafers used in low-power consumption IC apps.
2014-09-03	Samsung funds research for 7nm The South Korean tech giant is financing Pennsyvania State University's work on III-V, which explores FinFET fabrication using the combination of silicon and indium gallium arsenide.
2008-08-18	New process touts improved IC speed, power use Semiconductor wafer supplier IQE plc has beefed up its portfolio of manufacturing processes.
2015-03-17	New material tops silicon, graphene in electron mobility Scientists recently discovered a new material believed to possess electron mobility that is 200 times greater than that of graphene and more than 1,700 times that of crystalline silicon.
2015-04-16	Leading technologists talk about Moore's law It has been 50 years since Moore's law came to light, and now three top technologists share their thoughts pertaining to Moore's law as well as their take on its proponent, Gordon E. Moore.