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2002-06-03 Xilinx challenges Altera's Stratix
Xilinx Inc. claims its Virtex-II Pro, an answer to Altera's new PLD architecture, integrates three devices along with immersing hard IP blocks.
2009-03-20 Using the DLL Phase Offset Feature in Stratix II and HardCopy II Devices
This application note describes how to implement the delay-locked loop (DLL) phase offset feature with Altera's Stratix II and HardCopy II devices.
2009-01-27 Using the design security feature in Stratix III devices
As FPGAs start to play a role in larger and more critical system components, it is ever more important to protect the designs from unauthorized copying, reverse engineering, and tampering.
2009-01-12 Using DDR3 SDRAM in Stratix III and Stratix IV devices
DDR3 SDRAM is the latest generation of DDR SDRAM technology, with improvements that include lower power consumption, higher data bandwidth, enhanced signal quality with multiple on-die termination (ODT) selection and output driver impedance control.
2005-12-19 System General offers support for Altera Stratix II FPGAs
System General announced its device support for Altera's Stratix II EP2S15, EP2S30 and EP2S60 FPGAs in FBGA484 packages.
2008-05-28 Synopsys lends support for Altera Stratix IV FPGAs
Synopsys says that the FPGA synthesis solutions from its Synplicity Business Group, Synplify Pro and Synplify Premier, support the recently announced 40nm Stratix IV FPGAs from Altera.
2013-05-24 Stratix V GX FPGAs added to PCI-SIG integrators list
Altera's Stratix V GX FPGAs successfully passed all PCI-SIG compliance and interoperability tests, completing inclusion for Stratix V on all three generations of the Integrators Lists for PCIe.
2009-02-10 Stratix IV design guidelines
Altera Stratix IV FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications.
2007-03-05 Stratix III power management design guide
This document provides recommendations and guidelines for power management system design in systems featuring Altera Stratix III FPGAs.
2008-05-13 Stratix III FPGAs support SGMII on LVDS I/Os
Altera has rolled out its Stratix III FPGAs support Serial Gigabit Media Independent Interface on its LVDS I/Os.
2008-11-13 Stratix III FPGAs power ASIC prototyping board
The Dini Group has selected Altera Corp.'s Stratix III EP3SL340 FPGA, featuring 340K logic elements (LEs), in its DN7020K10, the industry's largest single-board FPGA-based prototyping engine.
2008-01-24 Stratix III FPGA features 340K logic elements
Altera says it has developed the industry's highest-density FPGA, the EP3SL340, which features 340,000 logic elements.
2008-02-22 Stratix III 340L FPGA powers GiDEL compute accelerator
GiDEL announced that the new PROCStarIII family of products is now available based on the Stratix III 340L from Altera.
2008-01-25 Stratix II GX FPGAs prop up 50Gbit/s SFI-5 interface
Altera Corp. has announced SERDES Framer Interface Level 5 (SFI-5) standard support in their Stratix II GX FPGAs with embedded transceivers, providing a 40-50Gbit/s interface for high-performance optical communications applications.
2006-03-28 Stratix FPGAs qualified for military sector
Altera's Stratix FPGA family has been qualified for military temperature requirements, ranging from -55C to 125C.
2010-04-21 Stratix FPGAs deliver up to 1.6Tbit/s serial switching
Altera Corp.'s 28nm high-end Stratix V FPGAs will offer up to 1.6Tbit/s of serial switching capability, 1.1 million logic elements and 53Mbit embedded memory.
2009-04-22 Stratix dev't kit eases high-speed interface testing
Altera Corp. has released the Stratix IV GX transceiver signal integrity development kit that allow engineers to prototype and test their high-speed interfaces quickly and easily.
2009-01-29 Power optimization in Stratix IV FPGAs
Stratix IV FPGAs deliver a high level of performance and power efficiency for high-end applications.
2005-01-26 New Stratix II member with 82 percent more LEs
Altera announced that it has shipped the largest and final member of the Stratix II FPGA family.
2002-11-12 MorethanIP cores support Altera Stratix FPGAs
Altera Corp. and MorethanIP GmbH have signed an agreement which provides Altera customers access to MorethanIP's portfolio of 10Gb Ethernet IP cores.
2006-11-28 Mentor announces synthesis support for Stratix III
Mentor Graphics has announced that its suite of advanced synthesis products supports the newly introduced Stratix III FPGAs from Altera Corp.
2003-10-31 LG 3G line to be powered by Altera Stratix
LG Electronics Inc. has selected Altera Corp.'s HardCopy Stratix devices for its 3G mobile comms infrastructure products.
2006-08-31 Key socket programmer rolls for Altera Stratix II FPGAs
System General has announced an AES key socket programming support for all Altera Stratix II FPGAs.
2013-10-31 Intel to fabricate Cortex-based Altera Stratix 10
Altera's deal in June to use Intel's 14nm FinFET process took an interesting twist when the FPGA designer announced today it will pack ARM's 64bit cores into its chips.
2009-02-27 Implementing UNH-IOL test suite compliance in Arria GX and Stratix II GX Gigabit Ethernet designs
This application note describes implementation details required for GIGE designs that do not use Altera's TSE MegaCore and require UNH-IOL compliance.
2009-12-29 Implementing the 40G/100G Ethernet protocol in Stratix IV devices
This application note describes how to implement a 40G/100G Ethernet line-side interface using Stratix IV GT devices.
2009-12-23 Implementing PLL reconfiguration in Stratix III devices
This application note describes the flow for implementing PLL reconfiguration in Stratix III devices.
2009-02-12 Implementing Bus LVDS interface in Cyclone III, Stratix III, and Stratix IV devices
This application note describes how to implement BLVDS interface in Cyclone III, Stratix III, and Stratix IV devices for high-performance multipoint application.
2005-09-08 How to interface DDR-II SRAMs with Stratix II devices
DDR-II SRAM devices offer enhanced timing margin and flexibility
2005-09-08 How to interface DDR-II SRAMs with Stratix II devices
DDR-II SRAM devices offer enhanced timing margin and flexibility
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