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2015-01-07 Using sub-threshold techniques for IC design
The use of sub-threshold techniques can be a powerful way to create circuits that consume dramatically less energy than those built using standard design practices.
2015-01-21 Sub-threshold design challenges low-power paradigm
Ambiq's Apollo family of 32bit ARM Cortex-M4F MCUs consume 5-10 times less power than comparable MCUs.
2013-09-23 Ambiq to sample out sub-threshold ARM MCUs by 2014
Ambiq is designing mixed-signal devices based on the Cortex-M0+ core from ARM that are tailored for emerging applications where power consumption is critical.
2015-12-29 Startup raises $16.5M for self-powering IoT systems
PsiKick has designed a proof-of-concept wireless sensor node system-chip using conventional EDA tools and a 130nm mixed-signal CMOS that operates with sub-threshold voltages.
2008-06-02 Working on India's analog dream
Notes Anand Valavi of Wipro Technologies, " We want to get to the point where people think if they have some state-of-the-art analog work to be done, India is a good place to do it."
2015-09-11 Upcoming IEEE conference to focus on key IoT tech
The emerging IoT market is looking for older nodes with lower development costs, broad range of process options, with many more players both at the foundry side and the design side.
2011-02-04 Tyndall scientists create n-type junctionless transistor
With a 50nm channel length and a cross-section of about 8nm x 12nm, the new junctionless transistor is 30 percent more energy-efficient and could represent simpler manufacturing processes for transistors.
2005-07-06 Transistor's gate stack structure uses Hf-based, high-k dielectric
NEC Corp. has announced the development of a transistor featuring a new gate stack structure using a Hf-based, high-k dielectric and a metal gate electrode
2005-01-20 Transistor's gate stack structure uses Hf-based high-k dielectric
NEC and NEC Electronics announced the development of a transistor that features a new gate stack structure using a Hf-based high-k dielectric and a metal gate electrode.
2014-09-12 Toshiba TFETs promise MCUs ultra-low power edge
The TFETs are fabricated using a quantum tunnelling principle to achieve ultra-low power LSI operation as a substitute to the conventional MOSFETs.
2006-02-13 TI, MIT, DARPA collaborate on 65nm SRAM
Researchers from Massachusetts Institute of Technology presented an ultra low power 256Kb SRAM test device manufactured in Texas Instruments' 65nm CMOS process.
2000-12-01 Technique probes deep-submicron test
This technology news article describes the latest Agilent Technology technique for conducting deep-submicron test schemes.
2008-02-18 Take a holistic approach to power management for mobile devices
Power management no longer remains a hardware-only problem; rather it has become a system problem that is being addressed by all engineers involved in the system design process. Power management decisions are being taken at both hardware and software level. Increasing focus towards system aspects of cellular phones compels designers to take a holistic and dynamic approach to power management to effectively decrease power consumption without degrading performance.
2015-03-12 Suppress jitter in Hall-effect sensor design
Find out how the signal path design influences the jitter performance of the output signal, and know the diverse design approaches taken to solve this problem.
2002-03-11 SoC stumbling blocks cataloged at DATE
It's not enough to be fast, efficient and technically proficient. Designers now must become Renaissance engineers.
2011-03-11 Singapore takes R&D initiatives to green its electronics
With increased awareness of climate change issues, green electronics will be the underlying theme for both manufacturers and consumers. Singapore is addressing these issues through R&D initiatives.
2008-04-16 Scale voltage to manage power consumption
As CMOS process technologies migrate from 90nm to 65nm and below and as chip densities increase, static and dynamic power consumption often rise above acceptable levels. Apply voltage-scaling techniques to manage both.
2014-10-10 Rising costs drive chip companies to alternate routes
The low cost of capital is fuelling M&A across all industries, and the rising cost and complexity of making chips is pouring gas on the fire in semiconductors.
2015-12-24 Recent revelations on non-volatile memory conduction
There is a continuing work at IBM Zurich that has just provided us with new and important insights into non-volatile memory, as well as an intriguing mystery. Read this to learn more.
2013-03-18 PVs still beat MEMS for energy harvest, says panel
The MEMS panel at the MEMS Executive Congress Europe discussed doubts regarding the potential of MEMS as energy harvesters while also being optimistic regarding the prosepects of the technology.
2005-04-07 Philips, Penn State refine surface potential transistor model
Scientists from Philips Research and the Pennsylvania State University have developed a model of MOSFET behavior based on the extensive use of the surface potential measurements.
2016-03-07 Phase change memory advances: Threshold switching
Here's a look at threshold switching as part of the effort to understand every detail of the conduction mechanisms associated with nano-metric sized phase change memory devices.
2004-04-14 New BSIM3 model aids high-voltage IC design
Silvaco has rolled out a High-Voltage IC Design tool suite for LCD drivers, TFT drivers and power management ICs.
2005-08-04 NEC develops low standby leakage technology using high-k material
Two NEC Corp. units have developed technology to lower standby power for mobile devices by combining high-k technology and a body-biasing scheme.
2016-01-08 Mixed-signal IC design: Forecasts for 2016
This article will examine the key trends, challenges, and emerging solutions in mixed-signal system design enablement, focusing on mixed-signal verification.
2015-03-26 MCU battle: Low power is the name of the game
Using the EEMBC ULPBench power benchmark, introduced last year, MCU vendors have become engaged in a game of leapfrog, announcing new products with ever-improving benchmark results.
2002-06-19 Materials transitions stalk CMOS scaling
With the transition to copper and low-k interconnects showing just how difficult changes in materials can be, technologists gathered at the Symposium on VLSI Technology to consider a brace of materials challenges?ranging from new gate oxides to SOI and strained-silicon channels.
2013-07-29 Making 3D NAND flash practical
Learn about the key features and benefits of SMArT scheme which is touted to open the 3D NAND flash era.
2008-06-24 Low power design for analog/mixed-signal IP
Power reduction and management techniques using multiple clock and power domains, dynamic voltage and frequency scaling and power gating are effective for digital circuits but for analog design, lowering power consumption must be considered early in the design phase.
2010-02-25 Junctionless transistor eases chip making
Scientists at the Tyndall National Institute have designed and fabricated what they claim is the first junctionless transistor that can help simplify chip manufacture.
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