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2015-03-12 Suppress jitter in Hall-effect sensor design
Find out how the signal path design influences the jitter performance of the output signal, and know the diverse design approaches taken to solve this problem
2005-03-08 TI oscillator buffers save space, minimize jitter
Texas Instruments introduced eight new high gain output oscillator buffers that enable designers to save space while also minimizing jitter and power consumption
2002-02-06 Tektronix releases world's first digital jitter analysis module
Claimed to be the world's first digital jitter analysis module, the OTS9200 is aimed at reducing the time per test and accelerate the production of 10Gbps SONET/SDH equipment for metro networks
2009-10-23 Techniques for evaluating deterministic jitter
This article discusses the effects of power supply noise interference on PLL-based clock generators and describes measurement techniques for evaluating the resulting deterministic jitter
2013-07-08 SyncE timing chips boast phase jitter below 300fs RMS
The IDT 82V3910 and 82V3911 are low-jitter, highly-versatile SyncE network timing solutions optimised for use in 10GBASE-R/10GBASE-W and 40GBASE-R applications
2002-10-23 SAW oscillator tuned to optical switching
The S3569 surface-mount SAW oscillator produces a low-voltage PECL output over the frequency range of 622.08MHz to 670 MHz for SONET/SDH and 10GbE apps.
2007-05-17 S/PDIF transceivers suppress jitter in audio band
Wolfson Microelectronics' WM8804 and WM8805 transceivers offer jitter suppression in S/PDIF audio data transfer
2014-12-03 OTN clock translator offers notable jitter performance
The ITU-T G.8251-compliant OTN ZL30169 integrates a digital phase locked loop, analogue PLL and EEPROM into a 5 x 5mm 32-pin QFN package to support increasing bandwidth requirements.
2014-11-19 Off-line switching power supply eliminates optocouplers
The InnoSwitch family from Power Integrations is geared for smart mobile device chargers and adapters for various applications that include STBs, networking equipment and computer peripherals.
2002-12-03 Maxim mux features 0.8ps maximum jitter
The MAX9384 LVPECL/PECL/LVECL/LVPECL 2:1 mux from Maxim Integrated Products exhibits a maximum jitter of 0.8ps
2002-12-18 Maxim LV clock drivers boast low jitter
Two new LVCMOS/LVPECL clock drivers/repeaters from Maxim offer 3ps maximum rms random jitter for apps that demand low pin-to-pin skew distribution
2015-07-10 Jitter concerns when selecting timing solutions
Determining the effects of jitter on the system, as well as defining the jitter budgets for the various sub-systems are the keys to optimising system performance
2008-11-03 Frequency synthesizer offers sub-picosecond jitter
Maxim introduces the MAX3678 low-jitter frequency synthesizer with nine LVPECL clock outputs and intelligent dynamic switching.
2010-11-10 FPGA meets 10G optical jitter performance
Xilinx Inc. rolls out FPGAs that support 40Gbps and 100Gbps line cards with flexible port configurations.
2014-11-12 Determine acceptable jitter level in embedded design
Learn about the nuances of clock jitter specifications, and know how to determine the acceptable level of jitter early on in the development cycle to prevent dire impact on end product release schedules
2007-09-06 Crosspoint switch has 10ps jitter at 3.125Gbps
National says its LVDS 4 x 4 crosspoint switch delivers the best jitter performance at 10ps typical at data transmission rates of up to 3.125Gbps
2014-09-17 Clock multiplier, jitter attenuator ICs target comms apps
The ZL30252 and ZL30253 from Microsemi give communication equipment customers a timing solution that meets industry-leading jitter performance imposed by the latest 100Gb/s PHY devices
2005-03-16 Buffers blend low jitter, low power
Texas Instruments introduced eight new high gain output oscillator buffers measuring 2-by-2-by-0.55mm, which minimize jitter and power consumption
2013-06-05 Address jitter, noise with DDR4 (Part 1
DDR4 specification provides a way for designers to allocate the system timing and noise budget between the controller, memory interconnect and the DRAM that is difficult, if not impossible to accomplish with other high-speed interfaces.
2016-03-31 Ultralow DCR sensing makes for higher efficiency in LTC7130
The constant frequency peak current mode synchronous step-down DC/DC converter from Linear Technology also reduces switching jitter in low DCR applications.
2003-11-11 Zarlink TDM family eases board-level design
The company has launched a family of mid-density TDM switching devices that simplifies board-level design
2013-09-24 Xilinx OTN solutions bridge gap between ASSP, ASIC
SmartCORE IP aims to deliver all programmable solutions needed to create intelligent 400G and Nx100G OTN solutions and OTN switching platforms with low latency, low jitter and high QoS requirements.
2006-06-09 Wintegra adds adaptive clock recovery access suite
Wintegra has announced that it has added adaptive clock recovery to its suite of multi-service access support.
2011-07-25 Understanding power issues in SDI products (Part 1)
Learn about the considerations to make when designing with analog and mixed-signal serial digital interface components.
2012-07-06 Third generation voltage regulators from International Rectifier
IR introduces third generation point-of-load voltage regulators for netcom, server and storage applications
2013-12-23 The lowdown on high-perf timing in board design
Know the various scenarios facing board designers when working with high-performance timing.
2004-09-30 PCI Express requires ATE strategy
As PCI Express becomes mainstream, IDMs and fabless companies require a new breed of production test strategies.
2003-03-05 Network processing group to expand benchmarking
The Network Processing Forum has released implementation agreements that expand its benchmarking efforts in the areas of Multi-Protocol Label Switching, as well as switching fabrics used with network processors
2007-09-10 LVDS crosspoint switch delivers 3.125Gbps
National Semiconductor's new LVDS 4 x 4 crosspoint switch delivers the what it claims to be the best jitter performance (10ps typical) at data transmission rates up to 3.125Gbps
2010-06-18 Clock cleaner IC eliminates unwanted noise
The Si5317 pin-controlled jitter cleaning clock IC provides jitter filtering to remove unwanted noise and produces low jitter outputs for a wide range of applications
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