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2006-02-14 New patterning synthesis solution for 65/45nm
Invarium unveiled DimensionPPC, a unified, full-chip process and proximity compensation product for patterning IC layouts at 65nm and below.
2000-05-01 Long road ahead for analog synthesis
It may be a bit like asking why can't women be more like men, but the question, "Why can't analog be more like digital?" is the most common complaint among engineers attempting to use analog design tools. Synthesis (the automatic generation of physical circuitry from a high-level language description) is one area where analog design departs drastically from digital
2003-12-09 EDA startup pioneers assertion-based synthesis
Startup Bluespec Inc. will preview an "assertion-based" synthesis technology next week that it describes as a new approach to chip design
2003-05-14 Synthesis engines' roll out to speed up PLL designs
Barcelona Design has developed synthesis "engines" that are capable of generating PLLs for 0.15?m and 90nm CMOS processes
2002-11-08 Synthesis-friendly RTL called key to first-pass design
To achieve first-pass timing closure on complex ASICs, designers must ensure their chip architecture design and RTL design are physical synthesis-friendly
2006-01-26 Synthesis tool combines advantages of flat, hierarchical design
It's one thing to design individual blocks for large systems-on-chip and another to tie them together into a working device. Sierra tackles the latter challenge with its Pinnacle Chip Assembly solution.
2008-05-09 Run practical power network synthesis
Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are commonly designed as custom switch cells of fixed sizes. The method described in this article avoids this unrealistic assumption and introduces the concept of a "fake via" to enable power network synthesis using existing EDA tools
2008-01-14 Processor combines ARM9 CPU, 3D graphics engine
Magnum Semiconductor Corp. announced the ZEVIO ZV1050 multimedia application processor, the latest member of its ZEVIO SoC line for cost-effective and power-sensitive applications in consumer entertainment and information applications.
2003-04-30 Magma folds synthesis into integrated tool suite
Magma Design Automation has unveiled the Blast Create, a single tool that combines silicon virtual prototyping, RTL, and analysis.
2009-09-03 DSP engine targets telecom, VoIP apps
Tensilica Inc. has introduced the ConnX D2 16bit dual-MAC (multiply accumulate) DSP engine for its proven Xtensa LX dataplane processor cores for SoC designs
2012-04-03 Developing NAND flash controller with high-level synthesis
Read about the application of a commercial HLS tool to a NAND flash controller with an error correction code block.
2013-02-22 Audio synthesis, noise suppression in vehicles
Audio synthesis and noise suppression solutions can contribute in compensating for the absence of engine noise and keeping sound levels down in the vehicle interior.
2005-06-01 Application engine synthesis offers new design approach
Application engines have become critical functionality enablers in SoCs for complex consumer devices
2008-09-02 Achieve efficiencies with algorithmic synthesis
Algorithmic synthesis moves the creation of application engines (algorithms on silicon) to a higher level of abstraction, giving significant time and cost savings
2004-06-11 EDA deals seen as engine of innovation
Most EDA innovation will continue to spring from startups rather than the R&D operations of public EDA companies, prompting large companies to acquire new emerging companies to stay competitive.
2008-04-29 New BlueCore5 platform allows hands-free control
CSR has announced that its BlueCore5-Multimedia platform now supports integrated speech synthesis, also known as text-to-speech (TTS), and speech recognition (SR) functionality
2004-06-09 Incentia releases runtime QOR for tool line
Incentia Design Systems released the 2004.05 version of its timing analysis, logic synthesis and physical synthesis software products
2010-11-10 FPGA design software updated
Lattice Diamond 1.1 extends support to MachXO and MachXO2 product families
2007-04-19 ESL tool targets algorithm for FPGA, ASIC devices
Although Synplicity Inc. left the ASIC synthesis market last year, the company is targeting ASIC designers once again with a new edition of its Synplify DSP product
2002-05-23 Atrenta adds logical prototyping to analysis tool
Atrenta Inc. has released a new add-on to its SpyGlass IC prototyping tool that it says will help engineers create a logical prototype of their SoC designs.
2006-09-01 Tool compiles C source code to RTL
CebaTech Inc. recently announced plans to offer both TCP/IP intellectual property (IP) and the C-language compiler that was used to create it.
2006-05-01 Synopsys adding to its DFM lineup
Included in Synopsys' yearend agenda is the addition of a dual-domain simulation product and a next-generation yield analysis tool to its DFM product family.
2003-10-01 SynApps customizes its tools for users
Following an unusual business model, SynApps Software Corp. leverages in-house technology to offer customized EDA tools that perform static timing analysis, synthesis, placement, clock tree synthesis and simulation
2002-01-17 Sensory speech recognition software features 10MIPS operation
Operating with as little as 10MIPS and 25KB of memory, the Voice Activation speech recognition engine is designed for mobile telephones, hands-free kits and VoIP infrastructure components
2007-05-30 Routing suite receives 45nm design update
Gearing up to deal with 45nm IC physical design challenges such as interconnect resistance, Sierra Design Automation Inc. this week is announcing three significant enhancements to its Olympus-SoC placement and routing suite.
2002-01-24 Plato adds RC extraction to IC router
Plato Design Systems Inc. has integrated an RC extraction engine and added other enhancements to a new version of its IC router
2004-06-01 Optimizer vows custom speed for standard blocks
Startup Zenasis Technologies says its cell-based timing-optimization tool can analyze blocks of up to 600Kgates.
2002-08-15 Mentor upgrades partitioning software
Mentor Graphics Corp. has updated the SpeedGate DSV in-circuit ASIC verification environment, to support multiple languages, and include distributed processing capabilities.
2005-02-01 Magma reveals next-gen IC design suite
Magma Design Automation introduced Cobra, an internal development effort that promises a number of technology breakthroughs.
2003-09-01 Improve the library, not the tools, to achieve timing closure
Combining the library approach with physical synthesis is an effective solution to extend the life and usage of older tools
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