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2013-12-23 Mentor to acquire Oasys' RTL physical synthesis platform
The move by Mentor seeks to help SoC/ASIC design teams to realize improved quality of results and faster turnaround time for today's complex SoCs, ASICs and IP blocks.
2010-06-25 A high-level synthesis methodology for complex FPGA
This article describes the implementation of Virtual Line Crossing Detection (VLCD) on an Altera Stratix II FPGA and the methodology we used
2002-09-16 Toshiba, Neolinear formulate new methodology for Soc design
Toshiba and Neolinear teams up to implement a new AMS design methodology that enables significant analog design reuse
2004-12-17 Toshiba uses Forte synthesis for next-gen design flow
Toshiba Corp. has chosen Forte Design Systems' Cynthesizer SystemC behavioral synthesis product for use in their SystemC design flow
2009-01-22 Synthesis tools' new versions promise better performance
Synfora Inc. has announced new versions of their PICO Extreme and PICO Extreme FPGA algorithmic synthesis design tools that will achieve higher performance and smaller area than the previous generation of the tools
2011-05-19 Synthesis tool improves functional coverage
NextOp has introduced its BugScope Assertion Synthesis that automatically generates high quality assertions and functional coverage properties in Verilog formats
2004-08-12 Synthesis suite targets unconventional designs
FTL's Merlin is a tool suite that includes behavioral synthesis from VHDL or SystemVerilog; analog synthesis from VHDL-AMS or Verilog-AMS; and analysis and simulation
2004-10-01 Synthesis suite targets unconventional designs
FTL Systems is quietly preparing a complete IC design solution, but this small, privately held company isn't about to go head-to-head against the big EDA vendors.
2008-06-16 Synfora extends synthesis technology to FPGAs
Synfora, specializing algorithmic synthesis tools used to design SoCs and FPGAs, recently announced the availability of PICO Extreme FPGA, which extends their algorithmic synthesis technology to FPGA devices
2007-07-11 RTL synthesis tool eases chip-level interconnect design
Claiming a new approach that helps solve problems with chip-level interconnect, Cadence Design Systems is announcing a new component of its RTL synthesis tool, the Cadence Logic Design Team Solution
2002-06-13 Quartus II, Precision Synthesis to support SDC format
Altera Corp. and Mentor Graphics Corp. have announced that their Quartus II design software and Precision Synthesis software products will support the Synopsys Design Constraint format used to define ASIC design constraints when using tools from multiple vendors
2005-12-15 Methodology kit addresses wireless design challenges
Cadence announced its RF Design Methodology Kit, which is designed to address key challenges in wireless design
2005-06-16 Methodology for DSP-based FPGA design
Here's a technique to solve productivity and design-quality issues that have previously plagued DSP developers.
2005-05-05 Mentor Graphics extends Catapult C synthesis product
Mentor Graphics Corp. announced extensions to its Catapult C synthesis algorithmic synthesis tool, an electronic system level (ESL) design tool
2007-09-27 Mentor fields vendor-independent FPGA synthesis tool
Mentor Graphics has released the Precision RTL Plus Synthesis, which significantly improves the way of designing FPGAs and dramatically increases designer productivity
2004-06-01 Embedded synthesis enhances high-density FPGA tools
Tools developed specifically for deep submicron programmable devices are emerging, enabling 100,000 gate and greater FPGAs to become mainstream choices.
2012-04-03 Developing NAND flash controller with high-level synthesis
Read about the application of a commercial HLS tool to a NAND flash controller with an error correction code block.
2012-04-30 Design for power methodology: From architectural plan to signoff
Here's a look at a holistic design for power methodology that spans from architectural decisions through front-end design to physical implementation and sign-off
2014-12-04 Calypto intros high-level synthesis tech to speed up design
The Catapult 8 with the configurable hierarchical design architecture is built on a completely revised architecture that expedites design and verification closure, pushing widespread adoption of HLS.
2012-11-28 Cadence synthesis tech eases Renesas ASIC design
The Encounter RTL Compiler claims to improve utilisation by 15 per cent, area reduction by 8.4 per cent, quick turnaround time and cost reduction for complex ASIC designs.
2008-09-02 Achieve efficiencies with algorithmic synthesis
Algorithmic synthesis moves the creation of application engines (algorithms on silicon) to a higher level of abstraction, giving significant time and cost savings
2007-04-19 ESL tool targets algorithm for FPGA, ASIC devices
Although Synplicity Inc. left the ASIC synthesis market last year, the company is targeting ASIC designers once again with a new edition of its Synplify DSP product
2005-07-15 Epson doubles productivity using Cadence RTL compiler
Japan-based electronics device provider Seiko Epson Corp. (Epson) disclosed that it has doubled in the production tapeout of high-volume LCD controller chip using Cadence Design Systems Inc.
2002-08-28 Xilinx overhauls FPGA software design package
A major upgrade of Xilinx Inc.'s Integrated Software Environment FPGA design tool package features new system-level design capabilities, improved performance, and new utilities to simplify FPGA design.
2004-03-15 User lauds unreleased Design Compiler version
A special pre-release version of Synopsys' Design Compiler synthesis tool is demonstrating huge improvements in runtime and memory capacity, according to an engineer who reviewed the tool for the E-Mail Synopsys Users Group
2006-09-01 Tool compiles C source code to RTL
CebaTech Inc. recently announced plans to offer both TCP/IP intellectual property (IP) and the C-language compiler that was used to create it.
2002-05-22 SYCS licenses Magma's Blast Chip
Synergetic Computing Systems has licensed Magma Design Automation Inc.'s Blast Chip for its combined RISC and DSP multiprocessor architecture called the SYNPUTER.
2011-09-01 Speeding up medical imaging process using FPGA
Read about the use of FPGA platform and a synthesis tool called Impulse C to speed up a statistical line of reaction estimation for a high-resolution PET scanner
2003-04-25 Ricoh to deploy Monterey design flow in Japan
Ricoh Co. Ltd has purchased an entire line of Monterey Design Systems' planning, prototyping, and implementation tools for immediate use in Japan.
2003-10-21 Researcher calls for new HDL approach for SoCs
A new approach to hardware design languages is needed in order to create a better "programmer's view" for SoC designs.
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