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2006-04-07 Xilinx beefs up AccelDSP Synthesis tool
Xilinx announced the immediate availability of the new AccelDSP Synthesis 8.1 tool and AccelWare DSP libraries of algorithmic intellectual property.
2005-02-18 Web downloadable design tool suite supports new LatticeEC FPGAs
Lattice announced the immediate availability of v4.2 of its web-downloadable ispLEVER-Starter programmable logic design tool suite
2003-04-23 Verplex tool now checks datapaths
Verplex Systems Inc. has released an add-on to its Conformal Logic Equivalence Checker that allows the tool to verify complex data path circuitry
2003-06-02 Verplex tool now checks data paths
Verplex Systems Inc. released an add-on to its Conformal Logic Equivalence Checker that allows the tool to flatten data path structures without requiring designers to identify boundaries and architectures
2005-09-02 UMC, EDA firm offer inductor synthesis
United Microelectronics Corp., a semiconductor foundry based in Taiwan, has collaborated with EDA software company Integrand Software Inc. (Berkeley Heights, New Jersey) to improve a virtual inductor library applicable to a UMC 0.13?m CMOS process.
2003-12-23 Tool promises parallelizing synthesis
Touting a new approach to parallelizing, high-level synthesis, the Center for Embedded Computer Systems at the University of California at Irvine has released its Spark synthesis tool to engineers. Available as a free download, Spark takes C-language input and produces register-transfer-level VHDL code.
2004-03-17 Tool pinpoints false paths, steers designers away
FishTail Design Automation is targeting what sounds like a small niche, but the company says the potential benefits of its technology are huge.
2006-09-01 Tool compiles C source code to RTL
CebaTech Inc. recently announced plans to offer both TCP/IP intellectual property (IP) and the C-language compiler that was used to create it.
2002-11-08 Synthesis-friendly RTL called key to first-pass design
To achieve first-pass timing closure on complex ASICs, designers must ensure their chip architecture design and RTL design are physical synthesis-friendly
2006-12-13 Synthesis tool meets complex CMP design rules
The new synthesis tool from Blaze DFM Inc. inserts dummy fill patterns into a design layout and is said to optimally meet complex CMP design rules without requiring complicated scripts.
2011-05-19 Synthesis tool improves functional coverage
NextOp has introduced its BugScope Assertion Synthesis that automatically generates high quality assertions and functional coverage properties in Verilog formats
2010-05-11 Synthesis tool handles complex design verification
NextOp is bridging design and verification with the introduction of an assertion-based verification solution to automatically generate functional coverage properties from testbench and RTL.
2006-12-06 Synthesis tool eases ANSI C code generation
By automatically generating C, Catalytic Inc.'s new synthesis tool claims to eliminate the traditional process of manual translation.
2006-01-26 Synthesis tool combines advantages of flat, hierarchical design
It's one thing to design individual blocks for large systems-on-chip and another to tie them together into a working device. Sierra tackles the latter challenge with its Pinnacle Chip Assembly solution.
2005-12-06 Synthesis tool boosts FPGA performance by 20%
Version 8.4 of Synplicity's Synplify Pro product is designed to provide additional performance-enhancing features for Lattice Semiconductor's FPGAs.
2004-03-16 Synthesis methods for ASIC, FPGA designs
Design methodologies that employ cross-implementation EDA technology such as the MultiPoint provide the flexibility to implement a design in the best possible medium.
2005-01-27 Synplicity upgrades FPGA synthesis
Synplicity released a new version of its Synplify Pro FPGA synthesis tool boasting major run time and quality of results improvements.
2004-09-17 Synplicity upgrades FPGA logic, physical synthesis tools
Synplicity announced the latest version of its FPGA logic synthesis and physical synthesis software solutions
2003-01-10 Synplicity revamps ASIC synthesis tool
Synplicity Inc. is stepping up the competition against Synopsys, Get2Chip, and Incentia with its latest Synplify ASIC.
2004-03-18 Synopsys takes another stab at FPGA synthesis
Synopsys has tweaked its Design Compiler ASIC synthesis tool to enable designers to use the same tools and potentially the same design flow for ASICs and FPGAs.
2003-03-06 Synopsys DFT tool receives core add-on
Synopsys has integrated the SoCBIST add-on to its DFT Compiler for the creation of IP cores.
2005-10-11 Software offers graph-based physical synthesis into FPGAs
Synplicity has expanded its Synplify family of FPGA synthesis tools with Synplify Premier software
2004-06-03 Siemens adopts Mentor Catapult C synthesis tool
Mentor Graphics Corp. announced that Siemens Information and Communications Networks has reduced C source to register transfer level (RTL) implementation time by 50 percent on a strategic project using their latest Catapult C synthesis tool.
2006-12-21 RTL synthesis tool speeds up run-time
Cadence Design Systems has released Encounter RTL Compiler version 6.2, which promises a 10 percent improvement in quality of silicon and a 30 to 50 percent run-time speedup.
2007-07-11 RTL synthesis tool eases chip-level interconnect design
Claiming a new approach that helps solve problems with chip-level interconnect, Cadence Design Systems is announcing a new component of its RTL synthesis tool, the Cadence Logic Design Team Solution.
2007-02-08 Reusable IP enhances ESL synthesis
Bluespec's AzureIP library brings reusable IP to an ESL synthesis tool that starts at a much higher level of abstraction and produces RTL code.
2004-05-17 QuickLogic FPGAs supported by Magma synthesis tool
QuickLogic has announced that Palace, the Magma physical synthesis tool for programmable logic devices, now supports its mWatt Eclipse II and Eclipse FPGA products.
2002-06-13 Quartus II, Precision Synthesis to support SDC format
Altera Corp. and Mentor Graphics Corp. have announced that their Quartus II design software and Precision Synthesis software products will support the Synopsys Design Constraint format used to define ASIC design constraints when using tools from multiple vendors
2001-06-15 Powerful low-cost synthesis for Actel ProASIC 500K family
This application note describes the LeonardoSpectrum ASIC/CPLD/PLD synthesis tool for the Actel ProASIC 500K devices.
2005-03-01 Physical synthesis in structured ASICs
How does a physical synthesis tool help ease front- and back-end design flow issues? Read on.
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