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2007-07-09 Verification tool for ARM-based wireless systems debuts
Mentor Graphics Corp. today extends support of iSolve emulation-based IP products for ARM processors to enable the high-speed verification of wireless and multimedia applications and reduce time to market
2008-06-02 Use system models for better verification
This article describes the system-level to RTL design and verification flow of a commercial graphics processing chip. In this flow, system models were developed to validate the arithmetic computation of video instructions and were then used to verify the RTL implementation using sequential logic equivalence checking.
2008-01-02 Perform integrated HW/SW verification
As the lines marking the responsibilities of HW/SW teams and who is responsible for implementation and debug are getting blurred, new methodologies must be adopted to effectively validate an entire IP or silicon solution. The ability to efficiently and optimally design, and perform system-level verification can result in a significant competitive advantage, especially as software solutions become expected deliverables along with complex IP or silicon
2012-08-30 Overcoming challenges for SoC verification team
Know the unique problems that SoC verification engineers face and the approach that provides them a level of automation similar to that enjoyed by block-level verification teams
2003-06-16 Memory verification needs fresh approach
By interpreting parameter values corresponding to the implementation structure, equivalence-checking comparisons between RT and transistor level can be easily accomplished.
2003-08-18 Memory overwhelms current verification techniques
Circuit simulation is unable to provide adequate functional verification coverage for memories
2010-07-21 Hitachi implements Cadence verification system
Transaction-based acceleration technology is being used to implement the system-level verification environment for Ethernet routing/switching products
2008-02-20 Functional verification platform is intelligent
Mentor Graphics has released the Questa Multiview Verification Components product and the inFact testbench automation tool
2014-07-10 Emulator runs pre-silicon verification of memory SoCs
The Veloce2 from Mentor Graphics is enables verification engineers to develop and stress test software and hardware on SoCs using HMC, LPDDR4, and eMMC 5.0
2004-02-04 EDA providers team on verification solutions
EDA providers Denali Software Inc. and CoWare have announced a partnership to address system-level verification of complex chip designs
2006-06-15 Cadence offers 'first' transaction-based system verification
Cadence unveils 'first' automated end-to-end transaction-based system verification and management solution
2003-08-13 ARM, Axis co-develop system-level verification flow
ARM Ltd and Axis Systems Inc. have signed an agreement to develop a fully integrated, system-level verification flow for ARM cores and the ARM PrimeXsys Platform
2003-11-24 ARM rolls out transaction-level SystemC models
ARM Ltd has announced the availability of the transaction-level SystemC models of its cores that are targeted for system-level verification.
2013-07-22 Virtual design, verification for e-Mobility
Learn how to address many of the emerging engineering challenges that carmakers now face.
2012-04-20 Verification platform geared for SoC, FPGA design
Mentor Graphics' Questa 10.1 release claims to increase productivity with regard to verification and boasts enhanced support of the Universal Verification Methodology
2007-08-29 Verification kit supports advanced techniques
Cadence Design Systems' new verification kit for SoC designs that aims to enable engineers to adopt advanced verification techniques with reduced risk and deployment effort
2002-03-14 Verification gets no respect, panel says
Verification gets no respect, according to participants in a "value of verification" panel at the International HDL Conference
2006-02-23 Tool generates verification plans from design specs
Severity One is starting to sell Relay, a tool that produces reusable, coverage-driven verification plans from textual specifications or user input through a graphical user interface
2005-06-22 Synopsys, IBM collaborate on PowerPC processor models
Synopsys announced fully synthesizable versions of IBM's PowerPC 405 and 440 processors as part of the DesignWare Star IP program.
2004-06-24 Synopsys tips system-level co-verification
Synopsys Inc. and embedded virtual-platform startup Virtio are jointly developing a system-level hardware-software co-verification solution that will allow designers to work from correlated models, the companies said.
2011-06-08 Simulation tool offers Xilinx FPGA verification
MathWorks announced the availability of its EDA Simulator Link 3.3 with new FPGA-in-the-loop capabilities for Xilinx FPGA development boards to help engineers verify their designs at hardware speeds.
2008-02-26 Rhines on EDA: End 'endless verification
Walden Rhines of Mentor Graphics calls for a combination of formal methods, TLM techniques and intelligent testbenches to lower the cost of design verification
2001-06-16 Real system-level design challenge: Hardware-firmware integration
For today's engineering co-design, the real system challenge is the hardware/firmware integration.
2004-08-02 Is verification really 70 percent
The oft-quoted statistic that functional verification takes 70 percent of the chip design cycle may be more myth than science
2005-04-12 IBM exec calls for system-level tools
Design automation needs to provide an integrated approach to system-level design, said John Darringer, manager for system-level design at IBM's T.J. Watson research center, in a keynote speech at the Electronic Design Processes (EDP) workshop
2016-01-04 Examining memory models
Know the qualities you should look for in memory models, and learn about a library touted to deliver the most comprehensive solution of this kind and supports any type of simulation environment
2007-05-16 Devising a system-level solution for EDA
To create a solution that offers a true enterprise-wide system-level flow, the industry must develop a comprehensive methodology that leverages much of its success in hardware development
2002-04-10 CoWare links system-level tool to Xilinx flow
Xilinx Inc. and CoWare Inc. are tailoring Co-Ware's N2C system-level design tool to create a design flow for Xilinx's newly announced Virtex-II systems-on-programmable-chips
2007-03-16 Use timing-accurate system-level models
A virtual system prototype provides a software simulation-based model of the electronic system that allows design teams to improve design productivity, reduce time-to-market and decrease risk.
2000-08-01 Design tips for high-performance verification
A flexible, high-speed modeling environment allows you to develop real-world test cases from high-level system models, captured live data, and interaction between system-level interfaces
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