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2001-05-01	Vendors should count silicon, not tapeout wins Tapeouts are certainly important. But they are not an end unto themselves, but, rather a milestone on the way to the goal of working silicon.
2011-06-07	STMicroelectronics completes 20nm chip tapeout The tapeout of STMicroelectronics' first 20nm technology demonstrator test chip has been successfully completed with Synopsys.
2004-01-01	Startup promises 'algorithm to tapeout' Synfora's Pico product line will let users create C-language algorithms for blocks such as MPEG or MP3 decoders.
2004-02-19	EDA startup AmmoCore claims first tapeout After a year and a half of silence, AmmoCore Inc. is announcing the first tapeout for Fabrix, its placement and optimization tool suite.
2015-10-09	Cadence, Imec announce 5nm test chip tapeout Imec and Cadence optimised design rules, libraries and place-and-route technology to obtain optimal power, performance and area (PPA) scaling via Cadence Innovus Implementation System.
2004-05-03	'Algorithm-to-tapeout' synthesis rolls Synfora has unveiled a tool that lets users design compute-intensive blocks from C-language algorithms.
2004-09-01	Synopsys CEO calls for DFM cooperation Synopsys CEO called on the design and fab communities to develop
2004-01-01	Startups taking over ESL It is very frequent that there a lot of new startup in ESL design, and ESL announcements from small, established EDA vendors.
2002-08-29	SiS adopts Cadence technology for graphics IC design Silicon Integrated Systems Corp. has standardized on Cadence Design Systems Inc.'s First Encounter, for the design of complex graphics ICs.
2011-12-07	Layout software speeds up chip finishing SpringSoft's Laker Blitz chip-level layout editor claims to load and export GDSII data files 5-20 times faster than conventional layout tools.
2005-07-01	Analog EDA firm tackles PLL noise Berkeley's PLL noise analyzer promises to shrink time-to-volume for discrete analog/RF chips and SoCs containing analog blocks.
2004-12-01	Trouble spinning in analog ICs Inability of analog chip designers to characterize the behavior of complex circuits prior to tapeout is a major obstacle.
2005-12-07	P.A. Semi's 65nm processor developed with Cadence platform Cadence said its Encounter digital IC design platform has helped P.A. Semi develop its new 65nm multicore PWRficient processor with a successful test-chip tapeout in March 2005.
2008-01-30	Matsushita taps Synopsys compiler for 45nm design Synopsys announced that its IC Compiler has been used in Matsushita Electric's 45nm SoC device tapeout.
2005-07-15	Epson doubles productivity using Cadence RTL compiler Japan-based electronics device provider Seiko Epson Corp. (Epson) disclosed that it has doubled in the production tapeout of high-volume LCD controller chip using Cadence Design Systems Inc.
2002-05-21	Chipmakers see early payoffs of design reuse In a testament to design-for-reuse, a 10-member Motorola Inc. design team took a chip to tapeout in a hectic two-and-a-half months, engineers told the Custom Integrated Circuits Conference.
2005-01-28	Cadence RTL compiler supports Sanyo production designs Cadence Design Systems Inc. revealed that Sanyo Electric Co. Ltd has achieved an important production tapeout with the Cadence Encounter digital IC design platform, including RTL compiler synthesis.
2007-03-15	Cadence platform enables Taiwan's first 65nm chip design Cadence Design announced that Global Unichip was the first Taiwan-based design company to complete a successful tapeout of a 65nm device with the use of Cadence Low-Power Solution and SoC Encounter GXL RTL-to-GDSII system.
2001-02-01	Behavioral modeling accelerates for OEM requirements This technical article describes the high-level behavioral modeling that can speed-up design along the road to tapeout by identifying architectural opportunities and pitfalls.
2011-03-21	Xilinx poised to catch Altera at 28nm Calling its Kintex 28nm device family a winner, analysts predict Xilinx would catch Altera at 28nm as the company is now sampling its second 28nm product, ahead of Altera.
2011-03-25	Xilinx FPGAs go down to 28nm Xilinx Inc.'s Kintex-7 K325T FPGAs are built with 28nm technology to meet the price and power performance needs of key applications.
2004-11-01	When custom ASICs aren't the answer Given their lower costs at high volumes, custom ASICs would be the logical choice. But that's often not the case.
2007-10-25	Virage Logic advances 65nm design Virage Logic is expanding its 65nm IP products, with an eye towards tackling today's complex IC design challenges.
2011-06-30	USB solution features built-in self-test Evatronix's USB high speed PHY IP is designed to complement the company's suite of USB 2.0 device and host controllers.
2006-06-27	UMC is getting 65nm interest According to major silicon foundry United Microelectronics Corp., it has been getting a lot of interest in 65nm designs.
2012-01-30	TSMC fires back at analysts Marced did acknowledge that each process node roll out has problems but said TSMC engineers rise to the challenges.
2013-04-15	TSMC FinFET production set in 2013 Company executives detailed the new processes and how they aim to get there and also gave an update on 3D chip stacks and their on-going ramp of today's 28nm process node.
2012-06-28	TI bets on China for MCU design TI's facility in China is not there just to support existing MCU products. Rather, it actually executes some MCU product line development from China.
2006-03-13	TI adopts multidisciplinary approach for 4G design Texas Instruments is using vertically oriented engineering teams to ensure the success of its fourth-generation wireless design and development efforts.
2007-07-11	The need for new post route analysis techniques Any new method to understand design manufacturability used by design teams, mask manufacturers and semiconductor manufacturers requires predictability, fast time to results and accuracy.