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2008-08-13 World's first 3D chip technology surfaces
The world's first 3D chip process is ready for licensing from the fabless semiconductor design house BeSang
2003-02-20 Velio chip supports backplanes at 6.25Gbps
Velio Communications' test chip implements the company's second generation of I/O core used primarily for switching fabrics.
2002-12-19 UMC, Xilinx ready for 90nm chip manufacturing in '03
United Microelectronics Corp. and Xilinx Inc. have announced that they are on track to produce Xilinx's latest family of programmable chips in 2H of 2003, utilizing UMC's 90nm chipmaking process technology.
2006-11-22 UMC produces 45nm SRAM chip
United Microelectronics Corp. has cleared a key 45nm process hurdle by producing an SRAM chip with a bit cell size of less than 0.25?m?
2004-02-02 Toolset eyes process test-chip design
Silicon Canvas released a platform for process test-chip development that is designed to help foundries create test chips to verify, optimize and calibrate silicon processes.
2003-12-10 Tool set eyes process test-chip design
Silicon Canvas Inc. will release a platform for process test-chip development that the company calls the first commercial product of its kind. The Laker T1 platform is designed to help foundries and integrated device manufacturers create test chips to verify, optimize and calibrate new silicon processes.
2002-03-12 Synopsys, UMC develop signal-integrity test chip
Synopsys and UMC announced they have developed the ATG-SI test chip for researching signal-integrity effects on designs developed in UMC's 0.13?m Fusion process.
2011-06-07 STMicroelectronics completes 20nm chip tapeout
The tapeout of STMicroelectronics' first 20nm technology demonstrator test chip has been successfully completed with Synopsys.
2004-02-23 Parallel clocking extends chip operating speed
NEC researchers have developed a parallel clocking approach for circuits that operate at 10GHz, which is capable of setting clock frequency separately from the operating frequency of a chip
2011-01-27 Nujira to unveil second-gen handset test chip
Nujira is announcing its second-generation handset test chip at Mobile World Congress (MWC) in Barcelona next month and the completion of an Envelope Tracking Processor IC for cellular network infrastructure.
2005-12-08 Japanese researchers unveil 3-D stack for chip integration
Japanese researchers have come up with a new three-dimensional integration technology called Super-Smart-Stack that uses a self-assembly technique to maintain chip alignment accuracy to within 1?m
2005-02-21 Intel claims first single-chip silicon laser based on SOI
In what could disrupt the photonics space, Intel Corp. on Wednesday (Feb. 16) described what it claims is the world's first silicon-based continuous-wave laser on a single chip - built around silicon-on-insulator (SOI) and other technologies
2005-02-23 Intel claims first single-chip silicon laser based on SOI
Intel described what it claims is the world's first silicon-based continuous-wave laser on a single chipbuild around SOI and other technologies
2006-11-10 Infineon test chip avoids vertical interconnect defects
Infineon claimed to be the 'first' to deliver the test chip for avoiding VIA defects in the production of highly integrated semiconductor circuits by a factor of 10.
2003-10-02 Infineon releases test chip for fault localization
Infineon Technologies AG has manufactured a test chip that enhances complex semiconductor design processes.
2011-12-16 Globalfoundries, ARM tape out 20nm chip
The tape out was a milestone for Globalfoundries' Technology Qualification Vehicle (TQV), which it has worked closely on with ARM.
2011-09-01 GlobalFoundries tests 20nm chip
GlobalFoundries has manufactured a 20nm test chip utilizing design tools from other design companies such as Cadence Design Systems, Magma Design Automation, Mentor Graphics and Synopsys.
2003-02-03 Faraday rolls 90nm-processed test chips
Faraday Technology Corp. has taped out test chips manufactured on UMC 90nm process, using design solutions supplied by Magma Design Automation Inc., including Blast Fusion and Blast Noise
2015-10-09 Cadence, Imec announce 5nm test chip tapeout
Imec and Cadence optimised design rules, libraries and place-and-route technology to obtain optimal power, performance and area (PPA) scaling via Cadence Innovus Implementation System.
2012-11-06 Cadence designs test chip for 14nm SOI FinFET
EDA vendor Cadence has come out with a test chip designed for checking parameters and IP at the 14nm node.
2002-09-30 ARM, SMIC to codevelop test IC for China market
ARM Ltd and Semiconductor Mfg Int. Corp. have signed an agreement to develop an ARM7TDMI microprocessor core-based test chip targeted for SMIC's 0.185m CMOS process.
2007-06-12 ARM to field verification IP for on-chip comms
ARM plc will start sampling to its lead partners the AMBA Adaptive Verification IP for on-chip communication during the third quarter
2003-06-05 Applied Materials develops 90nm interconnect test chip
The X Initiative, a semiconductor supply-chain consortium, has announced that Applied Materials Inc. has produced a 90nm test chip for X Architecture interconnect designs.
2004-02-27 Applied makes 65nm X-architecture test chip
Applied Materials and Cadence Design Systems have made a 65nm test chip using diagonal as well as traditional right-angle Manhattan interconnects.
2005-10-12 Amkor spin-off Integra focuses on test
Integra Technologies LLC, once part of Amkor Technology Inc., on Monday (Oct. 10) announced the commencement of its operations in the chip-testing sector
2008-02-28 AMD, IBM detail first 'full field' EUV chip
AMD and IBM have produced a working test chip utilizing EUV lithography for the critical first layer of metal connections across the entire chip.
2014-10-03 Working 14nm chip on display
Analysts initially said getting the 16nm and 14nm processes ready will be met with some challenges, since this process node is the first to use 3D transistors, but Samsung already has on display a 14nm FinFET device decoding video streams.
2005-04-14 Wireless PHY test software works in LabVIEW
SeaSolve Software's test suite is tightly coupled with existingand provensignal analyzer and signal generator hardware
2008-09-08 Wind River Workbench, On-Chip Debugging Edition
The introduction of 32bit and 64bit processor technologies has created new challenges that require an innovative approach to JTAG debug and analysis.
2007-07-19 WiMAX test system revs up production throughput
Agilent Technologies Inc. and GCT Semiconductor Inc. have partnered to jointly implement a WiMAX manufacturing test system for GCT's WiMAX chipsets
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