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2005-09-30 Synopsys testbench solution increases verification productivity
Synopsys announced Discovery Pioneer-NTB, a new SystemVerilog testbench automation tool that claims to increase verification productivity and improve the quality of complex SoC and IP designs.
2008-07-03 inFact tool adds distributed computing function
The latest version of Mentor's inFact tool now enables large simulations to be automatically distributed across up to 1,000 CPUs, extending non-redundant sequence generation to entire simulation server farms
2005-02-01 Tool vendors dispute report of downturn in ESL
Did the emerging ESL tools market take a
2003-07-29 Verisity ties testbench tool to Aptix accelerator
Verisity Ltd and Aptix said that Aptix will integrate its System Explorer hardware accelerator with Verisity's eCelerator testbench offering
2003-06-05 TransEDA debuts property verification tool
TransEDA has announced a property and assertion capture and validation tool at the 2003 Design Automation Conference
2010-05-11 Synthesis tool handles complex design verification
NextOp is bridging design and verification with the introduction of an assertion-based verification solution to automatically generate functional coverage properties from testbench and RTL
2004-05-24 CriticalBlue releases coprocessor synthesis tool
CriticalBlue is announcing the commercial release of its Cascade tool suite
2011-04-21 Verification tool offers advanced analysis, debug
Synopsys, Inc. has introduced the CustomExplorer Ultra mixed-signal verification environment that offers a comprehensive regression analysis.
2005-08-16 Tool gets a handle on voltage changes
As a chip designer for Intel Corp., Srikanth Jadcherla spent a lot of time working on multivoltage designs. Now he's launched an EDA startup, ArchPro Design Automation Inc., which is rolling out what it presents as the industry's first multivoltage RTL simulation product
2002-06-13 Dataquest predicts automation of RTL
The "automation of RTL" will be driven by the silicon virtual prototype and the intelligent testbench, according to Gary Smith, chief EDA analyst at Gartner Dataquest
2003-03-03 Synopsys upgrades VCS and Vera
The company has announced upgrades to its VCS 7.0 Verilog simulator and Vera testbench automation tool.
2005-07-29 Synopsys test methodologies verify SLE's chip developments
Synopsys Inc. announced that its VCS comprehensive RTL verification solution and Vera testbench automation tool have been adopted by ASIC design services provider Silicon Logic Engineering (SLE) to accelerate its chip development process.
2008-02-20 Functional verification platform is intelligent
Mentor Graphics has released the Questa Multiview Verification Components product and the inFact testbench automation tool.
2007-06-18 Define your verification plan with SystemVerilog
The adoption of constrained random testbenches, functional coverage and assertions fits seamlessly with embracing SystemVerilog. The value of these technologies is enhanced with an evolution of the verification planning process from simple test plans to VPA-driven verification plans.
2005-01-27 Verisity revenues grow as acquisition nears
Verification tool provider Verisity Ltd reported a 45 percent year-to-year revenue gain in the fourth quarter of 2004
2004-06-09 Verisity eyes 10x verification boost with VPA
Verisity hopes to address the growing complexity in IC development with a series of applications for both engineering-level and project-level problems.
2002-08-26 TransEDA offers PCI-X 2.0 verification IP
TransEDA PLC has put together a new verification bundle for designers wishing to create SoCs compliant with the PCI-X 2.0 standard.
2005-04-04 Verisity shareholders approve acquisition
Cadence Design Systems' estimated $285 million acquisition of verification process automation provider Verisity Ltd. has been approved by Verisity shareholders
2003-12-01 Verisity plans manager for verification
To build its franchise beyond testbench generation tools, Verisity Ltd is developing what it calls an "intelligent testbench.&quot
2002-09-18 Sugar language sweetens assertions
Three EDA vendors will announce support for the Sugar 2.0 formal property language, adding to a growing list of endorsements that suggests this new Accellera standard will be widely accepted.
2004-05-19 Lighthouse introduces synthesis tools for Verilog test
Promising to reduce testbench development time by up to 80 percent, startup Lighthouse Design Automation Inc. will introduce tools that synthesize Verilog testbenches from high-level specifications
2003-06-10 Formal tools won't replace simulation
Formal verification is a valuable adjunct to simulation, but not a replacement for it, according to panelists at the Design Automation Conference
2002-07-29 Fears ease as EDA suppliers report revenue increases
Easing fears that the EDA industry is riding the recession's downward slope, Verisity Ltd and Nassda Corp. have reported revenue growth for their recent fiscal quarters.
2003-01-03 EDA vendors brace for 90nm challenge in 2003
The ramp-up to 90nm chips will give the electronic design automation industry a strong focus in 2003, according to EDA industry executives and observers
2011-05-04 Design software supports UVM
SpringSoft has announced complete support for UVM with its Verdi Automated Debug System that enables UVM code and enhanced transaction-level analysis to ease debug of SystemVerilog testbenches.
2003-07-08 Axis Systems adds support for Verisity eCelerator
Axis Systems is integrating its XoC ESL co-verification tool and Xcite hardware accelerator with Verisity Ltd's eCelerator testbench portfolio
2002-06-14 Aldec extends RTL hardware accelerator capacity
Aldec Inc. has announced the availability of the Riviera IPT v12000 functional RTL hardware accelerator that handles up to 12 million FPGA gates.
2003-12-17 0-In Design tacks on static verification capability
The latest release of 0-In Design Automation Inc.'s assertion-based verification tool suite lets users run a design through debugging prior to simulation, potentially bringing the debug tools into the design cycle much earlier
2003-05-30 O-In offers 'unified coverage' metric
Claiming to offer the first metric that measures verification in both simulation and formal tools, 0-In Design Automation has announced a &quot:unified coverage" metric called structural coverage
2003-04-09 Cadence decries incompatible Verilog versions
The EDA industry is risking "disaster" with two separate and incompatible versions of Verilog unless the Accellera standards organization quickly hands over SystemVerilog 3.1 to the IEEE, according to Cadence Design Systems Inc.
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