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2003-09-01 Recycle RTL testbenches to verify IP models
Future work in the area of reusing RTL testbenches to verify TLM blocks will focus on fully automating the process, including automatic fault checking.
2009-05-22 Debugging stimulus generation in VMM, OVM testbenches
This article reviews the components of stimulus generation in the VMM and OVM environments, and outlines a typical layered stimulus solution. It also takes a look at the different capabilities available for debugging
2013-06-21 MIPI-protocol VIP provides exhaustive stress test
Mentor Graphics' MIPI VIP enables the use of stimuli generated by modern simulation testbenches, including SystemVerilog/UVM, and SystemC-based environments.
2004-05-19 Lighthouse introduces synthesis tools for Verilog test
Promising to reduce testbench development time by up to 80 percent, startup Lighthouse Design Automation Inc. will introduce tools that synthesize Verilog testbenches from high-level specifications.
2011-05-13 Software expands verification interoperability
Springsoft's Verdi debug software expands verification interoperability with complete UVM support enabling UVM code and better transaction-level analysis to ease debug of SystemVerilog testbenches.
2008-02-26 Rhines on EDA: End 'endless verification'
Walden Rhines of Mentor Graphics calls for a combination of formal methods, TLM techniques and intelligent testbenches to lower the cost of design verification.
2004-04-20 Mentor links SystemC to emulation
Mentor Graphics has announced a "transaction based" interface between SystemC testbenches and its VStation emulators.
2011-05-04 Design software supports UVM
SpringSoft has announced complete support for UVM with its Verdi Automated Debug System that enables UVM code and enhanced transaction-level analysis to ease debug of SystemVerilog testbenches.
2007-06-18 Define your verification plan with SystemVerilog
The adoption of constrained random testbenches, functional coverage and assertions fits seamlessly with embracing SystemVerilog. The value of these technologies is enhanced with an evolution of the verification planning process from simple test plans to VPA-driven verification plans.
2006-09-06 Website offers free open source C++ IC verification tools
Two engineers have launched a website with open-source tools that can help IC verification teams with C++ verification.
2006-11-29 Virtual prototype support rolls out
Bluespec Inc. will roll out within the week a new version of its Bluesim simulator that supports virtual prototyping for software development and hardware validation.
2003-07-29 Verisity ties testbench tool to Aptix accelerator
Verisity Ltd and Aptix said that Aptix will integrate its System Explorer hardware accelerator with Verisity's eCelerator testbench offering.
2004-03-25 Verisity adds accelerators, emulators to Axis line
Verisity Ltd plans to add dynamically programmable processors to the XoC, Xtreme, and Xcite acceleration and emulation products it acquired in the deal last month for Axis Systems Inc.
2003-09-09 Verilog won't diverge, user reps pledge
Although the IEEE and the Accellera standards organization appear to be heading in different directions with next-gen Verilog, IEEE 1364 Working Group and Accellera's SystemVerilog committee members said they won't allow incompatible standards to emerge.
2012-04-20 Verification platform geared for SoC, FPGA design
Mentor Graphics' Questa 10.1 release claims to increase productivity with regard to verification and boasts enhanced support of the Universal Verification Methodology.
2004-01-01 Verification platform for Jeda language rolls
Jeda Technologies released Jeda-X, a commercial product based on the Jeda hardware verification language.
2004-09-16 Unified data model brings signal integrity
Separate EDA environments and databases prevent analyzing signal integrity early in the design cycle, where it is most critical.
2002-08-26 TransEDA offers PCI-X 2.0 verification IP
TransEDA PLC has put together a new verification bundle for designers wishing to create SoCs compliant with the PCI-X 2.0 standard.
2016-05-16 The ideal union of PAM and Ethernet
Understand how various Ethernet speeds evolved through the utilisation of various pulse amplitude modulation (PAM) schemes.
2004-07-01 Testbench integrated on emulator
SpeXtreme lets designers implement testbench functions on the emulation hardware to speed verification.
2004-02-02 Synopsys, Cadence give nod to SystemVerilog changes
Enhancements based on feedbacks from vendors and users spotlighting some shortcomings in the current ver 3.1, will be implemented in SystemVerilog 3.1a.
2004-02-19 Synopsys, ARM to write SystemVerilog manual
Seeking to write the book on how to use SystemVerilog for verification, Synopsys Inc. and ARM Ltd. are working together on a SystemVerilog Verification Methodology Manual and hope to have it ready by June.
2005-09-30 Synopsys testbench solution increases verification productivity
Synopsys announced Discovery Pioneer-NTB, a new SystemVerilog testbench automation tool that claims to increase verification productivity and improve the quality of complex SoC and IP designs.
2006-03-22 Synopsys claims first complete SystemVerilog flow
Synopsys laid claim to being the first EDA vendor to provide a complete SystemVerilog flow, saying the language is now supported throughout its suite of design and verification products.
2004-06-01 Synopsys adds testbench features to VCS
Synopsys announced a new VCS release with added testbench capabilities that includes features derived from the company's Vera products.
2004-04-12 SynaptiCAD joins graphical debugging market
Offering a graphical debugging system that can control Verilog, VHDL, and C++ simulators, SynaptiCAD has announced BugHunter Pro.
2002-10-15 Swedish startup eases use of formal tools
Startup Safelogic is rolling out a formal property checker and a simulation "plug-in" for property monitoring.
2003-03-03 Summit tool beefs up SystemC
Summit Design Inc. launched its Visual Elite 3.1 which included FastC to better reach out to HDL designers.
2004-04-21 Startup's tool adds hardware validation
Carbon Design Systems has expanded the capabilities of its DesignPlayer models to perform hardware validation as well as presilicon software validation.
2003-05-02 Speeding up simulation
The paper presented by Rajesh Bawankule at the recent DVCon can help engineers to speed up verilog without spending a single penny.
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