Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > through-silicon vias

through-silicon vias Search results

?
?
total search135 articles
2007-04-25 Akita Elpida claims densest multichip package
Akita Elpida Memory Inc. said it has developed the world's densest multichip package with 20 stacked die in a package 1.4mm in thickness.
2014-08-11 Advanced packaging drives SPTS buyout
Orbotech, a provider of optical inspection equipment for PCBs and flat-panel displays, acquired SPTS, a semiconductor etching and deposition company, for $300 million.
2012-03-09 A*STAR, Applied Materials unveil 3D chip packaging R&D center
The new facility positions Singapore as a global leader in semiconductor R&D and is expected to help accelerate the development and adoption of 3D packaging technology globally.
2015-07-28 A closer look inside SK Hynix's 1st high bandwidth memory
SK Hynix's HBM has a 1,024-wide bus. It employs a base logic die as an interface between the four DRAM die stack and an interposer that supports both the HBM modules and the AMD GPU.
2014-02-06 3D TSV Summit underscores cost-effective production
From a maker's perspective, 3D IC production will only ramp up if the added costs for implementing TSVs and all the ensuing steps can be largely compensated by the IC performance benefits.
2013-11-12 3D IC success hinges on major foundries
3D chip stack technology is real and has users, but not high-volume ones, according to a panel of experts.
2014-12-12 3D IC adoption crucial to the entire TSV roadmap
Yole Developpement forecasted that the adoption of 3D IC technology, due to its many advantages, as well as its ability to enable heterogeneous integration, is being considered for many applications.
2014-05-08 3D chip-making technique utilises metallisation layers
The technique fabricates active devices interleaved between the metallisation layers atop a standard CMOS die, eliminating the expense of vertically stacked transistors or of stacking dies with TSVs.
2011-12-14 3-chip stack combines DRAM, SoCs
As an effort to push 3D integration, engineers used TSVs to link a wide I/O DRAM and two identical multicore SoCs in a device that can support 12.8GB/s of memory bandwidth.
2015-01-09 13MP image sensor boasts remarkable sensitivity
Aimed at smartphone camera applications, the AR1335 from ON Semi promises to deliver near-digital-still-camera quality with power consumption and footprint optimised for mobile devices.
2008-10-01 Stacked microprocessor system promises better performance
Take a different approach to chill. A group of researchers just did, resulting in what may be the most efficient heat dissipation possible for stacked microprocessors.
2007-10-18 Physical sensors drive MEMS consumerization wave (Part 1)
Benedetto Vigna notes that we are living today in the commercial era of MEMS Consumerization where microphones, motion and pressure sensors are the main actors. He believes this trend will continue for the next five years.
2014-07-01 MEMS startup focuses on Chinese ODMs for growth
Ben Lee, CEO of mCube, said it secured $37 million of Series C venture capital to enter phase three of its progress, and will target Chinese ODMs, not a design win from either Apple or Samsung.
2011-12-07 IME, Tezzaron develop "2.5D" interposer tech
A*STAR Institute of Microelectronics and Tezzaron Semiconductor aim to refine the design and manufacture of silicon interposers and standardize the process, flows, and process design kits.
2007-06-25 Designing in the age of 3D systems
The optimal utilization of the third dimension requires a careful design of the overall 3D system architecture.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top