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2007-04-17 IBM advances through-silicon via packaging tech
IBM Corp. announced it has made advances in through-silicon via packaging that will allow it to ship production chips using the new interconnect in 2008.
2011-02-25 Vendors keen on pushing mobile DRAM to higher speeds
While 800- or 1,066MHz LPDDR2 devices could serve as a bridge to next-gen technologies, they could also push out other next-gen candidates.
2011-04-21 STATS ChipPAC aims TSV expansion in Singapore
STATS ChipPAC is expanding its 300mm through silicon via (TSV) offering with the addition of mid-end manufacturing capabilities in Singapore.
2009-09-11 Singapore launches 3D TSV consortium
The Institute of Microelectronics has announced a 3D through-silicon via (TSV) consortium to boost next-generation 300mm wafer manufacturing capability.
2011-10-19 Recent developments in 3D integration
Here's a discussion on through-silicon via and mechanically flexible interconnect, and how these are being currently developed.
2010-03-22 Novellus, IBM launch 3D TSV program
Novellus Systems and IBM Corp. are opening a joint development program to design a manufacturing-worthy, copper-based, 3D semiconductor through-silicon via (TSV) process.
2011-04-06 Industry pushes TSV-based 3D chips development
Amid fears that IC scaling is becoming too costly for chipmakers, the IC industry is working to develop TSV-based 3D chips, and stack and connect devices in a 3D configuration using TSVs.
2010-12-09 ICs seen to scale via 3D TSV
Chip scaling is becoming harder and costlier entering into the sub-20nm realm, thus, the industry is looking for new materials, structures and processes, says a technologist from Samsung.
2009-12-17 IBM details 3D IC design challenges
IBM Corp. engineer John Knickerbocker offers five challenges for 3D devices based on TSVs.
2015-07-03 Examining 3D embedded substrate power packaging
Here is a look at 3D embedded substrate power packaging technologies, which will be increasingly deployed in everything from cell phones to hybrid electric vehicles.
2008-06-13 Alchimer picks Lenix as Korea representative for TSV
Alchimer, a provider of nanometric films for through-silicon via (TSV) metallization, has appointed Lenix as its representative in Korea.
2012-04-17 Addressing integration concerns with SiP technologies
Learn about the benefits and drawbacks of system-in-package technologies.
2012-12-20 A*STAR offers 2.5D through-silicon-interposer MPW service
The service is aimed at providing a cost-effective platform to do research and development prototyping and proof-of-concept in 2.5D TSI technology.
2011-09-27 A primer on 3D-IC design challenges
Know the 3D-IC design challenges such as system exploration, floorplanning, analysis, and design for test (DFT), and learn how designs will evolve as 3D-IC goes on to become a necessity for managing power, performance, form factor, and cost goals.
2007-04-25 Samsung develops 'first' all-DRAM stacked package using TSV tech
Samsung claims to develop the 'first' all-DRAM stacked memory package using 'through silicon via' technology, which will result in memory packages that are faster, smaller and consume less power.
2014-10-22 Samsung delivers 8Gbit 20nm DDR4 chips for servers
Beyond the 32GB modules, the new 8Gb chips will allow production of server modules with a maximum capacity of 128GB by applying 3D through silicon via (TSV) technology
2013-07-26 Metrology system configured for advanced packaging
Rudolph Technologies' metrology suite includes specially-designed configurations for wafer level packaging, 2.5D (interposer) and 3D ICs using through-silicon via (TSV) as interconnects.
2010-07-15 Applied boosts high-volume TSV manufacturing
Applied Materials Inc. announces the Applied Producer Avila system for high-volume manufacturing of stacked or 3D chips using through-silicon via (TSV) technology.
2010-12-15 3DS-IC group to fast-track TSV standards
SEMI worked with SEMATECH to launch the Three-Dimensional Stacked Integrated Circuits (3DS-IC) group to develop manufacturing standards for through-silicon via (TSV) technology.
2008-06-06 Will 3D through-silicon vias break into mainstream?
The 3D technology based on through-silicon vias technology took center stage at the IEEE 2008 International Interconnect Technology Conference but there is still no consensus just how the industry will bring the long-awaited technology into the mainstream.
2009-01-19 Ultrathin wafer bonding system installed in Taiwan lab
EV Group (EVG) has installed an EVG 500 series wafer-bonding system at Brewer Science Inc.'s Taiwan applications lab.
2008-04-30 TSMC IC design collaboration strategy stirs controversy
TSMC has unveiled a new and possibly controversial strategy that involves more collaboration in the early stages of the IC design process.
2011-04-11 TSMC enters chip-packaging arena
TSMC will soon open a bumping facility and offer silicon interposers and TSV technologies for 3D chips, but will remain focused on the foundry market and will not compete against subcontractors.
2014-02-19 Tips for cost-effective 3D IC production
Know how to distribute the cost-of-ownership across the supply chain.
2011-06-09 Test solution automates 3D IC deployment
Imec and Cadence has released a test solution that automates 3D stacked ICs deployment.
2012-01-16 STATS ChipPAC builds new factory
Once the new building is completed, STATS ChipPAC's combined manufacturing space in Singapore will increase from 55 277.30 to 73 579.21 square meters (595,000 to 792,000 square feet).
2011-02-03 Solutions model to latest 28-nm parasitic effects ratified
Synopsys collaborates with IMTAB members of IEEE-ISTO to ratify extensions to its Interconnect Technology Format, enabling parasitic extraction tools at 28nm and below process technologies.
2007-01-29 SiP lacks EDA tool support
System-in-package (SiP) may be an increasingly attractive alternative to SoCs, but EDA tool support is sorely lacking.
2011-05-13 SEMI forecasts strong growth for A-PAC chip industry
SEMI forecasts the fab spending in Southeast Asia to grow 43.8 percent year-on-year with positive demand in the electronics sector, especially for mobile devices.
2009-07-02 Sematech details tips for future IC scaling
IC scaling remains a challenge and to enable it, there is always brute-force lithography.
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