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total search254 articles
2004-08-16 Timing closure: Hybrid optimization to the rescue
Hybrid optimization combines ASIC cell-based design flow with transistor-level optimization to achieve improvement in timing closure.
2001-04-15 Timing closure in DSM design
Timing closure has taken center stage as the toughest challenge for today's deep-submicron designs. Subsequently, the problem of accurate timing verification has become more important than ever before. Can engineers continue to predict the timing of ICs prior to manufacturing as technologies continue to scale?
2003-12-26 Statistical static timing analysis ensures IC performance
Static timing analysis is one of the pilings upon which the whole edifice of modern IC design has been erected
2001-05-16 Sequence Design offers tool for timing closure
Sequence Design has combined different technologies in a "design closure" product that can optimize timing and signal integrity concurrently before and after routing.
2002-12-09 Researchers call for fundamental shift in timing analysis
Calling for a new approach to the design of digital circuits, researchers at the ACM/IEEE Tau workshop presented strong arguments for a move to statistical, or "probabilistic," timing analysis
2012-11-09 Remove pessimism and optimism in timing analysis
Pessimism could not only increase the time to fix the critical paths, but could also adversely affect other crucial parameters such as power and area.
2011-03-25 Memory controller IP enables timing closure, higher yield
Uniquify's Self-Calibrating Logic makes possible SoC designs that use its memory controller IP to automatically fine-tune critical timing parameters after the SoCs are installed in system boards
2003-09-01 Improve the library, not the tools, to achieve timing closure
Combining the library approach with physical synthesis is an effective solution to extend the life and usage of older tools.
2007-04-16 Fix timing closure problems
For designers of complex chips, the controlled, more predictable timing convergence of physical synthesis is of higher value
2004-06-01 EDA startup preps tools for RTL closure
Blue Pearl Software said its upcoming technology will identify and fix functional and DFT errors in RTL code, locate false paths and automatically generate timing constraints for synthesis
2009-03-17 Design Guidelines and Timing Closure Techniques for HardCopy ASICs
This application note covers topics from a timing closure perspective, for the successful migration to HardCopy ASICs from Altera's FPGAs
2013-05-22 Cadence's closure tool speeds chip designs to fabrication
The Tempus Timing Signoff Solution is a new approach to timing signoff tools that enables customers to shrink timing signoff closure and analysis for faster tape-out.
2004-02-11 Actel IDE enables faster timing closure
Actel Corp. has enhanced its Libero IDE to provide customers with faster timing closure when using the company's flash-based ProASIC Plus FPGAs.
2010-03-11 Achieving timing closure in basic (PMA direct) functional mode
This application note describes two methods to achieve timing closure for designs that use transceivers in Basic (PMA Direct) mode at higher data rates for Altera's Stratix IV GX or Stratix IV GT FPGAs.
2002-03-01 Achieving successful timing closure designs
This article details the design approach Morphics Technology utilizes to build a 5 million- to 15 million-gate chips for wireless signal processing that meets schedule, functionality and timing goals on first silicon
2013-08-27 Achieve successful timing closure
Find out how to derive design margins for successful timing closure.
2013-05-08 Synopsys IC compiler update speeds up design closure
The latest release features advanced optimisations to enable high-speed design, efficient implementation of final-stage engineering change orders and tape-out-proven support for FinFET-based processes.
2010-05-17 IC compiler enables faster design closure
Synopsys offers the IC Compiler 2010.03, a physical implementation solution delivering up to 2.5x faster performance on multicorner/multimode designs, and enhanced in-design technology for faster design closure
2012-05-17 EDA solutions claim 50% cut in time-to-closure
ICScape's tools have enabled over 100 tapeouts including applications for storage, wireless, baseband, data communications, multimedia, graphics, chipset and power management.
2004-04-16 Zenasis device offers up to four-fold runtime speed increase
The new timing optimization product from Zenasis brings cell-based designers a three to four-fold increase in runtime speed
2001-05-16 Questions for SystemC
OSCI is supposed to be an "open" and independent standards effort, but Synopsys still has total control over the license agreement.
2005-03-01 Physical synthesis in structured ASICs
How does a physical synthesis tool help ease front- and back-end design flow issues? Read on.
2002-05-16 Physical design implementation: Challenges and solutions
The article discusses several critical flow-related issues, including the way logical and physical variables are interleaved, that must be considered during physical design implementation.
2010-12-09 Magma preps Talus IC implementation tool for 20nm
The company claims Talus ver.1.2, a tool for routing, timing and extraction for SoC implementation enables engineers to implement 1 million to 1.5 million cells per day
2002-09-30 Magma Design: SoC design - Next challenge for Taiwan's IC sector
Over the past 10 years, Taiwan's semiconductor industry has seen tremendous growth.
2010-06-21 Implementing design preservation
Design preservation can reduce the implementation iterations during the timing closure phase by implementing just the changed modules.
2014-10-02 IEEE board approves OCV extensions to Liberty
The additions pushed forth by Synopsys give designers a modelling technique that may further cut timing margins for advanced process nodes such as FinFET, boosting timing closure turnaround-time.
2003-08-04 Cadence platform to be deployed by Global Unichip
Cadence Design Systems has announced that its Encounter Digital IC implementation platform has been selected by SoC design foundry Global Unichip Corp.
2005-01-27 Blue Pearl releases RTL optimizer
Blue Pearl Software has announced the release of its first product, Indigo RTL Analysis, for rapid functional closure
2002-01-01 Articulating hierarchical design for SoCs
The unified flow for complex designs, complete with hierarchical design capabilities, is an intuitively pleasing proposition.
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