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2007-05-08 Measuring phase, delay errors accurately in I/Q modulators
This Application Note describes a method to accurately measure internal and external phase and timing errors for a high performance direct I/Q modulator
2015-10-15 Logic analyser supports up to 4Gb/s debugging data rates
Keysight unveiled a logic analyser module that claims to deliver the industry's highest-data-rate state mode, highest timing mode (10GHz) and deepest memory depth (up to 400MB
2004-11-16 Linear Tech unveils 'industry's fastest silicon oscillator'
Touted by Linear Tech as the industry's fastest, this oscillator provides a simple, compact and robust timing solution for FPGAs, CPLDs, microprocessors and DSPs
2011-02-14 LeCroy oscilloscope tips 4GHz bandwidth
LeCroy Corp.'s WaveRunner 6 Zi oscilloscopes provide offset and timebase delay adjustment to allow signal and amplifier performance assessment and zooming on vertical and horizontal signal characteristics
2012-10-02 Jackson Labs Technologies touts complete GPSDO reference
The LC_XO 10MHz frequency and timing reference integrates a GPS receiver, power supplies and an ovenized, disciplined crystal oscillator in a sub 1 x 1in footprint
2008-04-24 Interfacing the MCP2122 to the host controller
This application note will discuss methods with which to interface the MCP2122 to a host controller and how to use the PICmicro MCU's CCP and Timer2 modules to generate the 16XCLK signal
2005-09-08 How to interface DDR-II SRAMs with Stratix II devices
DDR-II SRAM devices offer enhanced timing margin and flexibility
2005-09-08 How to interface DDR-II SRAMs with Stratix II devices
DDR-II SRAM devices offer enhanced timing margin and flexibility
2007-10-01 High-end memory interface needs FPGAs
As designers of high-performance systems strive to achieve higher bandwidth while meeting critical timing margins, a performance bottleneck standing in their way is the memory interface. New silicon features, along with hardware-verified reference designs, have overcome those challenges. Additionally, engineers must follow some basic rules to improve design cycle time
2016-01-12 Evaluating phase difference with correlation
Despite having the proper tool, we still need to use special techniques to get accurate phase measurements. Read on to know how to perform measurement that meets the timing requirements of your application
2006-08-09 Electronics driver suits next-gen memory devices
Semtech unveiled wht it touts as the first off-the-shelf quad-pin electronics driver with the performance and differential signal capability required for testing next-generation, high-speed memory devices such as DDR III
2008-03-31 DisplayPort receiver debuts for flat-panel displays
IDT has announced the availability of a DisplayPort receiver and timing controller device for inclusion in flat-panel displays for monitors, notebooks and LCD TVs
2012-02-29 Designing high frequency synchronizer with programmable MTBF features
Read about a high frequency synchronizer circuit with programmable mean-time-between-failure capabilities that is well suited for high frequency clock gating and input signal synchronization applications
2008-01-16 Design versatile high-speed ADCs
The high-speed ADC is the bridge between the analog and digital hardware, and many times it is placed in the responsibility of an all-digital or all-analog hardware designer. When that happens, the programmability has easier acceptance with the digital hardware designer, but it can save the day for an analog hardware designer who failed to set up the digital timing or signal integrity properly.
2006-03-17 Deep-memory oscilloscope platforms probe automotive FlexRay
Yokogawa Electric Corp. announces that it has developed the DL7400 Series FlexRay Signal Analyzers
2004-04-28 Datel ADC offers -95dB peak harmonic, 93dB SNR
Datel's ADS-953 optimizes signal return paths and provides internal, local decoupling to obtain a -95dB peak harmonic specification
2006-09-20 CPRI Serdes delivers 800ps delay calibration accuracy
National said its new CPRI Serdes is the first to guarantee 800ps delay calibration measurement accuracy and exceed all CPRI interface signal voltage and jitter requirements
2000-09-27 Configurable logic for wireless communications: Carrier and symbol synchronization
Software-defined radios (SDR) are highly configurable hardware platforms that provide the technology for realizing the rapidly expanding third (and future) generation digital wireless infrastructure. This paper is about carrier and timing synchronization in SDRs using FPGA-based signal processors.
2012-02-15 Comparator operates from 2.5-5.5V single supply
The AD8469 from Analog Devices features a -0.2V to 5.7V input signal range and TTL- and CMOS-compatible output drivers
2005-07-19 CMOS IC acts as analog front end
ProTek Analog released a mixed-signal CMOS monolithic device that integrates analog-to-digital converter conversion operations on a single chip
2014-09-17 Clock multiplier, jitter attenuator ICs target comms apps
The ZL30252 and ZL30253 from Microsemi give communication equipment customers a timing solution that meets industry-leading jitter performance imposed by the latest 100Gb/s PHY devices
2006-04-19 Clock generators target low-skew apps
Exar Corp. added a new family of clock generators to its clock and timing solution portfolio
2002-03-20 Cadence upgrades PCB tool flows
Cadence Design Systems has made major upgrades to its Studio and Expert series PCB design flows, adding capabilities to its SpecctraQuest Signal Integrity Expert, Allegro layout tool, and Specctra autorouter
2002-05-22 Cadence overhauls IC implementation suite
Aiming to speed timing closure and signal integrity analysis, Cadence Design Systems Inc. this week will announce an across-the-board update to its SP&R (synthesis, place and route) IC implementation suite.
2016-05-18 Benefits of adding isolation to LVDS interfaces
Adding isolation to LVDS interfaces provides a transparent solution that can be inserted into existing signal chains for high-speed and precision measurement and control applications
2005-12-20 ATE pin-driver chip provides differential drive and receive
Semtech is releasing its E7725 dual-channel driver and window comparator, which is billed as the first component to combine both signal drive and receive capabilities capable of driving and receiving in either single-ended or fully differential modes
2003-08-08 Aspex adopts Cadence solutions
Aspex Technology, a provider of signal processing solutions in silicon, has decided to deploy Cadence Design Systems' IC verification solutions
2009-05-12 Analysis: MIPS-Chipidea not a good mix
MIPS Technologies Inc., which in August 2007 bought Chipidea, a Portuguese analog and mixed-signal IP company, announced May 8 that it has divested its analog business group to Synopsys Inc. in an all-cash transaction for $22 million, effective immediately
2008-11-19 Analog on 45 nm treated with trepidation by senior engineer at ICCAD panel
It is possible to build robust high performance analog/mixed-signal on these leading edge digital CMOS technologies. And I have production silicon to prove my point
2002-07-17 Altera beefs up PLD software with ASIC flow, pushbutton utilities
Altera Corp. has upgraded its Quartus II PLD design software with new timing-closure capabilities and other features aimed at both novice and expert designers
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