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2002-09-05 Agere adopts Nassda simulator tool
Agere Systems has selected Nassda Corp.'s HSIM hierarchical full-chip simulator and analysis tool for advanced timing analysis of clock trees and memory characterization of its ASIC solutions
2005-12-15 AFE captures HD content in camcorders
Analog Devices launched the flagship device in a family of AFEs for HD image/video processing apps with a low-voltage differential signaling interface that is said to boost signal conversion performance by 30 percent
2003-05-19 Aeroflex selects Nassda verification tool
Aeroflex Microelectronic Solutions has adopted Nassda Corp.'s HSIM full-chip simulator and analysis tool for verification of its memories and mixed-signal designs in Aeroflex's IC families for the aerospace and defense markets
2013-06-05 Address jitter, noise with DDR4 (Part 1)
DDR4 specification provides a way for designers to allocate the system timing and noise budget between the controller, memory interconnect and the DRAM that is difficult, if not impossible to accomplish with other high-speed interfaces
2014-04-02 5G Wi-Fi SoC locates indoor position
The Wi-Fi chip from Broadcom is equipped with AccuLocate technology that employs fine timing measurement (FTM), enabling precise indoor positioning regardless of environmental factors
2004-10-05 System level design is here, Synopsys CTO says
System level design is happening now but it remains to be seen whether it will become EDA's next big thing.
2006-12-13 Synthesis tool meets complex CMP design rules
The new synthesis tool from Blaze DFM Inc. inserts dummy fill patterns into a design layout and is said to optimally meet complex CMP design rules without requiring complicated scripts.
2004-03-01 Starc to release Starcad-21 design methodology
Semiconductor Technology Academic Research Center will release v1 of a chip design methodology that covers silicon implementation from RTL to GDSII.
2004-05-14 Silicon modeling in the nanometer era
With 90nm in production and 65nm on the horizon, designs face increasing challenges: finer line widths, longer interconnect, more routing layers and more analog content.
2002-06-05 RTL-to-GDSII flow shows signs of maturity
The RTL-to-GDSII design flow will take center stage at next week's Design Automation Conference in New Orleans, as several vendors show new technologies intended to solidify an all-in-one flow.
2011-08-09 RIO platform features Intel Core i7 processor
National Instruments has released the cRIO-908x multicore CompactRIO systems and small Single-Board RIO devices featuring an Intel Core i7 dual-core processor.
2003-09-16 Register-transfer level design handoff is ready
Shrinking process nodes and tightened purse strings have made the venerable "gate-level design sign-off" unacceptable.
2003-09-16 Redefining design for yield, manufacturability
By adopting a more design-driven approach to production, many of the yield and manufacturing issues daunting the semiconductor industry can be addressed before they even occur.
2002-09-30 ON Semi clock driver suits Itanium platform
ON Semiconductor's MC100EP809 1:9 3.3V differential HSTL/PECL to HSTL clock driver features LVTTL clock select and enable.
2002-04-04 NI data-acquisition modules delivers 1MSa/s per channel
National Instruments has released the NI 6731 and NI 6733 16-bit PCI data acquisition modules that deliver 1MSa/s per channel, making them suitable for applications such as stimulus-response testing of devices that require frequency excitation.
2007-02-09 Macro modeling offers temporal, spatial modeling
Sequence Design's SMMART algorithm with temporal and spatial modeling addresses the issues of data size, prohibitive runtimes and memory footprint that are often the cause of failures in current transistor-based macro-modeling solutions.
2002-06-07 iS3 designs video processor on Avant! Astro
Integrated Semiconductor Supply Solutions Ltd has successfully taped out a 0.135m 125MHz video processor SoC, with 1-million-gate standard cells over a MGb of memory and analog macrocells, using Avant!'s Astro physical design solution.
2006-04-17 IC design flow integrated
Synopsys offers its customers the Pilot Design Environment, an integrated RTL-to-GDSII design system tailored to each customer's design infrastructure.
2011-10-13 Hardware enables high-performance inspection apps
NI has introduced a new hardware that helps create more convenient applications for inspection and embedded imaging.
2006-06-01 Give PCB computer-aided design its due
PCB CAD gets no respect. With about 12 percent of overall EDA industry revenue, it is marked by sluggish growth, little or no startup activity and few announcements of new technology.
2002-08-21 Fulcrum IC heats asynchronous design debate
A coolly tantalizing alternative to the latest approaches to blazing IC performance is expected to cut this week's sweltering heat at the Hot Chips conference.
2005-12-22 Faraday tapes out ASIC production chips with Cadence platform
Cadence announced that Faraday has taped out ten 130nm ASIC production chips with the Cadence Encounter digital IC design platform.
2005-01-03 Convergence of EDA technologies: Key to silicon success
The 2005 technical outlook for EDA demands robust design, verification and DFM solutions that produce quality silicon in a timely fashion at the lowest possible cost.
2006-12-04 Clear Shape offers electrical DFM analysis solution
Clear Shape Technologies has announced OutPerform, said to be the first complete and silicon-correlated electrical DFM analysis and optimization product to enable designers using sub-90nm processes to control the impact of lithography, mask, etch, RET, OPC and CMP effects on their chip parameters.
2003-08-15 Cadence platforms adopted by China-based IC design center
Cadence Design Systems Inc. has announced that China Suzhou CAS IC Design Center (SZ-CAS ICDC) has employed Cadence EDA platforms in its IC design platform.
2003-03-26 Automation tool speeds physical-design flow
ReShape Inc. claims that its physical-design-automation system allows designers to turn around production layouts of multimillion-gate SoC in 24h.
2011-09-27 A primer on 3D-IC design challenges
Know the 3D-IC design challenges such as system exploration, floorplanning, analysis, and design for test (DFT), and learn how designs will evolve as 3D-IC goes on to become a necessity for managing power, performance, form factor, and cost goals.
2010-09-22 “Reality? project characterizes ARM926 for inherent variability at 32nm
An IMEC-led project, called “Reality?, has conducted a characterization of an ARM926 core for the statistical variability that is inherent at the 32nm manufacturing process node. The research project, set up in 2008, has cost about $5.8 million.
2004-04-01 Zuken revamps PCB prototyping tool
Enhancements to the latest version of Zuken's PCB virtual prototyping tool, Hot-Stage 4.2, allow verification of complete electronic systems.
2005-08-29 ZTEC's 90MHz digital scope plug-ins play in PCI, PXI
ZTEC will be making its newest PC-hosted digital storage scope plug-in available in both PCI Extensions for Instrumentation flavors
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