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2009-03-02 Verification tools receive upgrades
Jasper Design Automation's ActiveDesign with behavioral indexing is an IC design tool billed as enabling design engineers to capture and preserve intended design behavior as it is being implemented.
2007-01-15 Let metrics help with verification
While the entire EDA industry is jumping on the coverage-driven bandwagon, clamoring for universal coverage databases and espousing the benefits of this "new" technology, one question arises. Are you making the most of all the metrics that are available to you today?
2002-11-07 IC layout tools grow while front-ends decline in '01
IC implementation toolsets and IC layout tools experienced phenomenal growth in 2001, while front-end tools such as logic synthesis faltered, according to a new report by Gartner Dataquest
2006-12-20 eInfochips verification component supports Mentor's Questa
A component that provides building blocks for efficient design-under-test in module and system-level verification for Mentor Graphics' Questa Vanguard program, including assertion testing, is now available from eInfochips Inc
2007-03-16 CPF-compliant tools aim for low power
Cadence Design Systems Inc. has added the Common Power Format to its existing logic design, verification and implementation tools.
2006-07-07 Xilinx unveils design tools for 65nm Virtex-5 FPGAs
Xilinx has announced the latest release of its design solution, the 8.2i ISE tool suite, now supporting the company's newest line of 65nm Virtex-5 domain-optimized FPGAs.
2007-08-17 Xilinx teams with EDA giants on 65nm FPGA verification
Xilinx has announced a collaboration with three major EDA companies to address the challenges of 65nm ultrahigh-capacity FPGA design verification
2005-05-09 Xilinx introduces new design tools for its DSPs
Xilinx introduced new design tools aimed at easing the implementation of high sample rate or multi-channel signal processing designs onto Xilinx DSP devices
2010-05-18 Wipro taps Mentor tools to reduce design time
Mentor Graphics Corp. and Wipro Technologies are partnering to continue to enable time-to-market and first-time right solutions to their global product engineering customers.
2006-09-06 Website offers free open source C++ IC verification tools
Two engineers have launched a website with open-source tools that can help IC verification teams with C++ verification.
2013-07-22 Virtual design, verification for e-Mobility
Learn how to address many of the emerging engineering challenges that carmakers now face.
2003-07-30 Verplex upgrades formal-verification line
On the verge of closing its sale to Cadence, Verplex is releasing an upgrade to its Conformal line of equivalence checkers.
2003-12-01 Verisity plans manager for verification
To build its franchise beyond testbench generation tools, Verisity Ltd is developing what it calls an "intelligent testbench.&quot
2004-06-09 Verisity eyes 10x verification boost with VPA
Verisity hopes to address the growing complexity in IC development with a series of applications for both engineering-level and project-level problems.
2003-09-24 Verification, test providers form outsourcing body
Six providers of services and tools for IC verification and test have banded together to form Expert Services and Tools for Semiconductors (ESTS).
2009-01-21 Verification tool provides step-by-step approach
OneSpin Solutions has amended its software and packaged it in a way that supports a step-by-step approach for beginners.
2007-07-09 Verification tool for ARM-based wireless systems debuts
Mentor Graphics Corp. today extends support of iSolve emulation-based IP products for ARM processors to enable the high-speed verification of wireless and multimedia applications and reduce time to market
2002-03-11 Verification tool enables rapid ASIC prototyping
Designed for creating ASIC and SoC prototypes using off-the-shelf FPGAs, the SpeedGate Direct System Verification environment addresses all hardware prototype creation and verification challenges
2012-04-20 Verification platform geared for SoC, FPGA design
Mentor Graphics' Questa 10.1 release claims to increase productivity with regard to verification and boasts enhanced support of the Universal Verification Methodology
2007-08-29 Verification kit supports advanced techniques
Cadence Design Systems' new verification kit for SoC designs that aims to enable engineers to adopt advanced verification techniques with reduced risk and deployment effort
2002-03-14 Verification gets no respect, panel says
Verification gets no respect, according to participants in a "value of verification" panel at the International HDL Conference
2001-04-15 Verification firm starts partners program
Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry
2011-02-07 Verification design flow connects third-party PCB tools
AWR has released an ODB++ PCB layout verification design flow for connecting third-party tools with its software solutions.
2007-01-31 Verification box exceeds 200MHz speeds
Gidel Ltd's Proc_SoC verification box claims to exceed verification speeds of 200MHz, thanks to a direct FPGA-to-FPGA interconnect scheme
2005-02-08 V6 automation tools speed SoC, embedded system design
Tensilica announced its V6 suite of automation tools, which significantly speed the design of major blocks in SoC design
2008-06-02 Use system models for better verification
This article describes the system-level to RTL design and verification flow of a commercial graphics processing chip. In this flow, system models were developed to validate the arithmetic computation of video instructions and were then used to verify the RTL implementation using sequential logic equivalence checking
2013-06-04 TSMC certifies Mentor EDA tools for 16nm FinFET
Mentor Graphics design and verification tools get certified for TSMC's 16nm FinFET process node. The companies also detailed their continued collaboration on 20nm physical verification kit optimisations.
2004-06-02 TransEDA releases new code coverage tools
TransEDA released a new tool for specification coverage and impact analysis, as well as a new "coverability analysis" option to its VN-Cover code coverage tool.
2002-08-26 TransEDA offers PCI-X 2.0 verification IP
TransEDA PLC has put together a new verification bundle for designers wishing to create SoCs compliant with the PCI-X 2.0 standard
2002-04-22 TransEDA licenses formal-verification technology from SRI
Making a concerted effort to be seen as more than a simulation add-on tool vendor, TransEDA plc has licensed raw formal-verification technology from Stanford Research Institute and plans to turn this know-how into formal and semiformal verification tools within a year.
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