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2013-07-22 Virtual design, verification for e-Mobility
Learn how to address many of the emerging engineering challenges that carmakers now face
2002-03-11 Verification tool enables rapid ASIC prototyping
Designed for creating ASIC and SoC prototypes using off-the-shelf FPGAs, the SpeedGate Direct System Verification environment addresses all hardware prototype creation and verification challenges.
2011-11-03 Perform assertion-based verification in mixed-signal design
Understand how assertion-based verification can address the challenges in analog/mixed-signal verification.
2010-01-15 Parallel language, early verification to drive 2010 success
According Mathworks India Pvt. Ltd managing director, Kishore Rao, parallel language and early verification with Model-Based Design will serve as cornerstones of engineering success in 2010
2011-10-24 Overcome challenges of ASIC/SoC prototyping with FPGAs
Learn about FPGA-based prototyping and the various factors that must be taken into account to successfully implement a prototyping strategy.
2004-12-01 Methodology sought for assertion-based verification
Silicon IP providers and creators seek guidelines on how to use assertions effectively, aside from the standard protocols.
2015-05-15 Enhancing analogue design verification using UVM
In this article, we explore an efficient, reusable analogue and mixed-signal verification approach using the Universal Verification Methodology
2001-03-27 Design Issues And Verification Challenges For Home Networks
This paper looks into some of the challenging questions and considerations when choosing the right processor for the Home Network application design.
2002-02-16 Dense wires snarl verification plans
This technical news article describes how the new deep-submicron silicon technology not only assists in implementing increasingly complex SoC designs but also introduces new verification challenges to designers everywhere.
2006-06-15 Cadence offers 'first' transaction-based system verification
Cadence unveils 'first' automated end-to-end transaction-based system verification and management solution
2006-12-06 Cadence India taps 13 new partners for verification alliance
Thirteen companies have joined the Verification Alliance Program of Cadence Design Systems (India) Pte Ltd, a global partner network of consulting companies focused on verification consulting services, verification IP development and training for Cadence customers
2009-10-05 Braving software-to-silicon verification challenges at 45nm
Software-to-silicon verification holds immense challenges at 45nm and beyond for system designers and tool vendors, with multiple paradigm shifts converging at the same time.
2008-06-05 ARM, Renesas, Synopsys draft low-power verification methodology
Synopsys Inc., ARM and Renesas Technology have collaborated to define the industry's first methodology to address the rapidly increasing complexity of low power verification
2013-01-02 Apply formal methods to power-aware verification
Read about an apps approach for implementing formal methods to power-aware verification
2006-04-18 Aldec solution increases network-based design verification
Aldec's new mixed-language solution promises to dramatically increase network-based design verification
2007-08-17 Xilinx teams with EDA giants on 65nm FPGA verification
Xilinx has announced a collaboration with three major EDA companies to address the challenges of 65nm ultrahigh-capacity FPGA design verification.
2006-10-10 VSIA forms verification IP quality workgroup
VSIA has formed a quality workgroup to create a verification IP quality worksheet that will address the challenges facing designers as they evaluate and implement standard verification IP components.
2007-07-09 Verification tool for ARM-based wireless systems debuts
Mentor Graphics Corp. today extends support of iSolve emulation-based IP products for ARM processors to enable the high-speed verification of wireless and multimedia applications and reduce time to market
2007-08-29 Verification kit supports advanced techniques
Cadence Design Systems' new verification kit for SoC designs that aims to enable engineers to adopt advanced verification techniques with reduced risk and deployment effort
2008-08-07 Two firms tie up to boost LTE protocol verification
In verifying interoperability between their respective products, Rohde & Schwarz and Qasara have announced their partnership in examining the compatibility of 3GPP LTE Virtual Tester and LTE compliant UE protocol stack.
2008-10-09 TSMC, Mentor team on advanced physical verification
TSMC and Mentor Graphics have collaborated on physical verification solutions leveraging a new feature of the Calibre nmDRC product called "Equation-Based DRC
2007-03-16 Take distinctive approach to IC verification
Richard Goering spoke with Hooman Moshar about Broadcom's distinctive approach to IC verification
2013-02-04 Tackling the challenges of transition to DDR4
Know the key technical challenges designers face in transitioning to DDR4
2005-05-02 Tackling physical verification below 90nm
The article reviews the key challenges of physical verification below 90nm and the methodologies needed to tackle them
2005-02-07 Synopsys verification tools to face tough IP design challenges
Chipidea has licensed key tools included in Synopsys Inc.'s Galaxy design and Discovery verification platforms to address tough IP design challenges.
2014-03-07 Synopsys unveils verification compiler sol'n
The Verification Compiler is a portfolio of integrated, next-generation verification technologies that include advanced debug, static and formal verification, simulation, verification IP and coverage closure
2004-06-24 Synopsys tips system-level co-verification
Synopsys Inc. and embedded virtual-platform startup Virtio are jointly developing a system-level hardware-software co-verification solution that will allow designers to work from correlated models, the companies said
2003-06-27 Synopsys strengthens verification efforts with acquisition
Synopsys Inc. has acquired InnoLogic Systems Inc., a provider of memory and full-custom equivalence checking technology.
2008-07-01 Synopsys gears up for 'techonomic' challenges
According to chairman and CEO of Synopsys Aart de Geus: There's a trade-off between innovation, execution and collaboration. You can execute, but if you don't collaborate with the right people, you have nothing.
2010-01-22 Solving today's problem of SoC verification
As more complex, mixed-signal SoC designs continue to stress verification methodologies and schedules, designers need new approaches in solving today's test challenges. Mixed-signal verification presents a unique challenge as the analog portion of the design requires highly accurate and time-consuming, analog simulation.
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