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What does IC design verification mean?
IC design verification refers to the process of determining whether or not the design of a product, of a given development phase, satisfies the conditions imposed from the start.
total search1903 articles
2009-03-02 Verification tools receive upgrades
Jasper Design Automation's ActiveDesign with behavioral indexing is an IC design tool billed as enabling design engineers to capture and preserve intended design behavior as it is being implemented
2002-03-11 Verification tool enables rapid ASIC prototyping
Designed for creating ASIC and SoC prototypes using off-the-shelf FPGAs, the SpeedGate Direct System Verification environment addresses all hardware prototype creation and verification challenges
2011-02-07 Verification design flow connects third-party PCB tools
AWR has released an ODB++ PCB layout verification design flow for connecting third-party tools with its software solutions.
2007-02-21 SystemVerilog falls short for design
SystemVerilog is widely applied to verification, however, design use lags due to concerns about tool support.
2006-08-18 Realtek, Cadence collaborate on formal verification design
Cadence Design and Realtek Semiconductor announced that they have collaborated to successfully reduce the risk of functional errors on its pilot multi-supply voltage design
2007-03-19 Plan your verification process with SystemVerilog
The best way for the verification team to match the automatic tests with their corresponding design features is via functional coverage metrics.
2007-09-17 Optimal use of assertions in verification
Assertions provide an efficient way of improving overall design cycle productivity by cutting verification time. Here are some tips in the optimal use of assertions in verification.
2007-11-19 Mindtree acquires TES IC design arm in India
Mindtree Consulting has bought Purple Vision, the IC design services subsidiary of French electronics design company TES Electronic Solutions SA
2004-03-12 Mentor Graphics works on China's chip design industry
Mentor Graphics Corp. has signed a memorandum of understanding (MoU) with China's Ministry of Education (MOE) to help the country boost its IC design engineering talent pool and overall industry growth
2007-03-16 Manage verification with success
Successful verification management requires good analysis of the specification, an awareness of the scope of the job at hand, and a firm decision on what coverage models and metrics to track. Here are some of the basic do's and don'ts to keep in mind
2008-08-01 Looking beyond advanced design geometries
With the presence of the design geometries between 1000nm and 1nm, we can start deploying 32nm flows and find the solutions of the transitional barriers between 32nm and 22nm. Design verification plays a vital role in reducing the design cost and improving the yield of the new products and product platforms.
2008-12-24 Dev't tool enables fast verification
IAR Systems has launched the IAR visualSTATE 6.20 that offers improved speed and memory efficiency, enabling rapid verification of more complex designs
2010-02-19 Dealing with formal verification constraints
Formal model checkers are indispensable, complementing simulation for block-level verification in an ever-challenging design environment. Constraints make a formal tool tick.
2004-02-02 Changing face of chip design
Spurred by growing complexity, electronic system-level design startups and tools are emerging at a rapid rate
2005-09-15 Cadence offers shorter AMS design cycle
The AMS Methodology Kit from Cadence promises to enable analog mixed-signal designers of wireless, wired and consumer electronics devices to achieve shorter, more predictable design cycles while creating reusable AMS blocks
2004-09-03 Cadence emphasizes solutions in design tech symposium
As part of a promotional campaign of its portfolio in Southeast Asia, Cadence Design Systems showcased different versions of its electronics design software solutions in a design technology symposium held in Manila, Philippines, in Aug. 24
2007-04-02 Address verification issues with scalable methods
This article examines how scalable verification, design for verification, and strategies that include abstraction, assertion-based techniques, and improved debugging methods address the fundamental challenges facing design teams.
2014-06-05 Accellera updates Verilog-AMS with verification, modelling
The enhanced features of Verilog-AMS 2.4 include supply sensitive connect modules, an analogue event type to enable efficient electrical-to-real conversion and current checker modules.
2007-01-16 Design-with-test' for low-power devices
A new methodology called design with test in which tools are deeply integrated and power consumption is highly considered during testing will be key in ensuring the continued success of low-power products
2008-04-21 XtremeDSP ver10.1 improves DSP, ESL design
Xilinx has made available versions 10.1 of the System Generator for DSP tool and the AccelDSP synthesis tool, the development environment delivered by the Xilinx XtremeDSP solution.
2007-02-05 Xilinx upgrades free ISE Webpack design suite
Xilinx has announced the immediate availability of the ISE WebPACK 9.1i release, the latest version of the company's free downloadable programmable logic design suite
2006-11-06 Xilinx unveils new design solution for Virtex-5 LXT
Xilinx announced the availability of a complete logic design solution including an update to its ISE design tools for their newest Virtex-5 LXT Platform FPGAs
2006-07-07 Xilinx unveils design tools for 65nm Virtex-5 FPGAs
Xilinx has announced the latest release of its design solution, the 8.2i ISE tool suite, now supporting the company's newest line of 65nm Virtex-5 domain-optimized FPGAs
2007-08-17 Xilinx teams with EDA giants on 65nm FPGA verification
Xilinx has announced a collaboration with three major EDA companies to address the challenges of 65nm ultrahigh-capacity FPGA design verification.
2004-03-08 Xilinx rolls out latest FPGA design tool version
Xilinx has release the latest version of its real-time debug and verification software for FPGA design.
2002-08-28 Xilinx overhauls FPGA software design package
A major upgrade of Xilinx Inc.'s Integrated Software Environment FPGA design tool package features new system-level design capabilities, improved performance, and new utilities to simplify FPGA design
2013-12-05 Xilinx outs comprehensive functional safety design package
The company's functional safety package includes a TUV SUD certified design methodology and tools that promise to increase design productivity and reduce certification risks
2005-05-09 Xilinx introduces new design tools for its DSPs
Xilinx introduced new design tools aimed at easing the implementation of high sample rate or multi-channel signal processing designs onto Xilinx DSP devices
2002-08-27 Xilinx design tool integrates IBM bus analyzer
Xilinx Inc. will begin shipment next month of the ChipScore Pro v5.1i logic debug and verification tool that features IBM's CoreConnect integrated bus analyzer cores, core insertion tools, and an analyzer interface
2006-06-29 Xilinx delivers design solution for 65nm FPGAs
Xilinx has released the 8.2i Integrated Software Environment (ISE) design solution supporting the company's 65nm Virtex-5 FPGAs
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