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2008-02-18 Why we need a new analog design flow
Analog-mixed signal designers need a first-time right design methodology now. Why is this familiar cry more urgent and probably truest this time?
2003-12-01 Verisity plans manager for verification
To build its franchise beyond testbench generation tools, Verisity Ltd is developing what it calls an "intelligent testbench."
2008-06-02 Use system models for better verification
This article describes the system-level to RTL design and verification flow of a commercial graphics processing chip. In this flow, system models were developed to validate the arithmetic computation of video instructions and were then used to verify the RTL implementation using sequential logic equivalence checking.
2003-07-09 Toshiba uses Tharas devices on verification flow
Toshiba Corp. has selected Tharas Systems' Hammer systems and the Hammer Accelerator Farm to be deployed into its DFT verification flow.
2007-09-20 Taiwan's MediaTek adopts Mentor's formal verification tech
Mentor Graphics announced that Taiwan's MediaTek has selected the 0-In formal verification technology to make it an integral part of its verification flow for their next generation design projects.
2010-05-11 Synthesis tool handles complex design verification
NextOp is bridging design and verification with the introduction of an assertion-based verification solution to automatically generate functional coverage properties from testbench and RTL
2014-03-07 Synopsys unveils verification compiler sol'n
The Verification Compiler is a portfolio of integrated, next-generation verification technologies that include advanced debug, static and formal verification, simulation, verification IP and coverage closure
2005-01-20 Synopsys develops reference design flow with China's chip foundry
Synopsys Inc. and Grace Semiconductor Mfg Corp., an IC foundry in Shanghai, China, have jointly developed a reference design flow for Grace's 180nm processes
2011-05-16 Springsoft software adds advanced verification tech
Springsoft has integrated an advanced technology platform to its Certitude Functional Qualification System that will enable broader deployment of verification qualification methodologies
2005-03-28 Renesas integrates Mentor's 0-In for assertion based verification flow
Renesas Technology Corp. has completed the integration of Mentor Graphics Corp.'s 0-In assertion synthesis technology and assertion-based verification flows with Renesas' LogicBench rapid prototyping system
2003-03-05 Mentor Graphics to develop FPGA verification solution for Thales
Mentor Graphics Corp. has entered into a technology relationship with Xilinx Inc. and Thales Communications to develop a new FPGA verification flow to meet Thales' requirements for its next-generation products.
2003-06-05 Matsushita unit uses Tharas system for IC verification
Panasonic System Solutions Co., a division of Matsushita Electric Ind. Co. Ltd, has adopted Tharas Systems Inc.'s Hammer to enhance its verification flow.
2003-03-10 Ikanos selects Tharas tool for chip verification flow
Broadband access vendor Ikanos Communications Inc. has incorporated Tharas Systems Inc.'s Hammer into its functional verification flow.
2006-12-21 IC verification users satisfied, survey says
Sixty percent of chip designers say they are satisfied with their IC verification environments according to a survey of more than 600 engineers sponsored by Emulation and Verification Engineering
2008-02-20 Functional verification platform is intelligent
Mentor Graphics has released the Questa Multiview Verification Components product and the inFact testbench automation tool
2002-10-02 FTD adopts Cadence design flow
FTD Technology Pte Ltd has selected Cadence Design Systems Pte Ltd's front-to-back design and verification flow as its primary platform for digital, analog, mixed-signal, and RF IC design.
2011-05-23 Four transactors expand verification family
EVE introduces four vertical solutions, further expanding its ZeBu hardware-assisted verification family into computer/peripherals, embedded processors, networking and video markets
2005-12-06 Forte, Summit team up on design and verification flow
Forte Design Systems and Summit Design announced their collaboration to deliver an integrated solution that combines the strengths of the Vista SystemC IDE and Cynthesizer SystemC synthesis products.
2011-10-05 Debug platform eases SoC design, verification
SpringSoft's open platform allows the creation and sharing of custom applications through the company's debug system.
2014-04-22 Cadence seeks comprehensive verification with Jasper
The combination of Cadence's and Jasper's technologies will result in an inclusive metric-driven verification approach that unites formal and dynamic techniques, accommodating engineers who increasingly adopt formal analysis to complement traditional verification methods
2003-08-13 ARM, Axis co-develop system-level verification flow
ARM Ltd and Axis Systems Inc. have signed an agreement to develop a fully integrated, system-level verification flow for ARM cores and the ARM PrimeXsys Platform.
2013-01-02 Apply formal methods to power-aware verification
Read about an apps approach for implementing formal methods to power-aware verification
2011-09-01 Accelerate processor verification through testbench infrastructure reuse
Find out how specialised processor verification IP can eliminate historical development and maintenance commitments
2002-09-23 0-In Design: A preferred approach for verification
Companies designing complex multimillion gate ASICs recognize functional verification as one of the largest problems facing design teams
2003-12-17 0-In Design tacks on static verification capability
The latest release of 0-In Design Automation Inc.'s assertion-based verification tool suite lets users run a design through debugging prior to simulation, potentially bringing the debug tools into the design cycle much earlier
2007-08-17 Xilinx teams with EDA giants on 65nm FPGA verification
Xilinx has announced a collaboration with three major EDA companies to address the challenges of 65nm ultrahigh-capacity FPGA design verification
2005-12-16 Wrestling functional verification
Experts have differing views on how the design process can be improved so as to diminish the need for verification
2007-08-02 Winbond adopts Cadence emulator to ease verification
Cadence Design Systems announced that Winbond Israel has adopted the Cadence Incisive Palladium emulator system for its advanced system-level verification needs
2002-05-24 VIA adopts Avant! Star-SimXT for SoC design verification
VIA Technologies Inc., a developer of PC core logic chipsets, microprocessors, multimedia and communications chips, has selected Avant! Corp.'s Star-SimXT simulator for sign-off verification of its SoC designs
2007-08-29 Verification kit supports advanced techniques
Cadence Design Systems' new verification kit for SoC designs that aims to enable engineers to adopt advanced verification techniques with reduced risk and deployment effort
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